DS90UB964-Q1: Video interface，FPDLINK III

Hello Jun,

Is the FPGA providing a PCLK to the 913? What is the operating mode of the 913? Also what is the frequency of the PCLK? Can you share logic captures of the CMOS PCLK, HS/VS, signals as well as the same signals from the FPGA to compare?

Best Regards,

Casey 

Thank you for your reply！

1 Yes，FPGA provides PCLK

2 The 913 register is configured by the host through IIC.But the configuration is the same as the 913 in CMOS.It should be external clock mode，the clock is 48MHz，and the divided 24MHz is used for CMOS input.

3 The PCLK = 72MHz，The video is 1280 X 720  RAW12.

4 Yes See attached for more details

Hello Jun,

Can you please measure the PCLK output from the FPGA to compare against the CMOS imager? Also it would be good to label the traces for the FPGA case to easily compare. If you attach the .logic files I can also take a look more closely at those. 

Best Regards,

Casey 

Because ub913 is an external clock mode.The external clock is given by FPGA. I think it is the problem here. I will do the PCB experiment again.Thank you!

Hello Jun,

Ok thank you for the update - please let us know if any additional support is needed 

Best Regards,

Casey

After testing, the external crystal ub964 still can't be locked.Could it be the power supply? CMOS is powered by the host through fpdlink, and ours is powered by FPGA system for ub913.Or is it caused by PCB design?

I use ub913 sub board in CMOS + FPGA, 964 can be locked.I'm confused！