Hi,
What is the REFCLK sequencing requirements?
I notice in section 7.4.4 of the datasheet it says: "REFCLK should be applied to the DS90UB954-Q1 only when the supply rails are above minimum levels"
Then it looks like in Figure 55 that REFCLK is being applied before the supply rails are above minimum levels (REFCLK applied as VDD starts to ramp up). What is the correct sequencing?
I also notice the DS90UB954-Q1 I2C does not ACK when I have a 26MHz REFCLK applied. However it does ACK when I remove the REFCLK (REFCLK pin is open). I am using the ASEDV-26.000MHZ-LR-T as a 26MHz REFCLK. I must be missing something in the datasheet - why is it unresponsive when the 26MHz REFCLK is applied?
See a scope capture of REFCLK below. Note the device is operating in VDD_SEL=LOW, and VDDIO = 1.8V.
Thanks,
Nicholas