I don't like interfacing CML levels on DIN inputs. How about using OUTPOL as a mod input for modest speeds (<1MHz)? What is the best solution to ensure the deterministic state of the data input buffer?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I don't like interfacing CML levels on DIN inputs. How about using OUTPOL as a mod input for modest speeds (<1MHz)? What is the best solution to ensure the deterministic state of the data input buffer?
Hi Eugene,
The modulation signal is actually routed through the path: DIN+/- to Input buffer to Current Modulator to the MOD+/- pins. The OUTPOL (LVTTL input pin) is only meant for simply changing the polarity of this modulation signal output at the o/p pins MOD+/-.
Also, the ONET4211LD is designed for high-speed applications, with data rates between 155Mbps and 4.25Gbps. The device may work at speeds < 1Mbps but the performance is not guaranteed at such low speeds.
Thanks,
Sri
Sri,
You don't have to explain how DINs are routed - it is clear from the datasheet block diagram. It is no brainer that changing polarity of the modulation signal (while their inputs are held at a predetermined state) has the same effect on modulation. My question is still open: will OUTPOL work up to 1MHz and how to place DINs at a predetermined state (say, DIN+ is "1" and DIN- is "0", or the opposite...). Will 5k resistor to GND on any of these inputs be sufficient?