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ONET4211LD: Common mode input voltage for DIN inputs

Part Number: ONET4211LD

Is there any data about Common mode input voltage for differential inputs or recommended high and low input voltages. The datasheet doesn't provide such information.

Thanks! 

  • Hi Michael,

    You can either AC couple or DC couple to DIN+/-.

    If you AC couple, please bear in mind minimum differential input is 200mV while maximum differential input is 1600mV. AC coupling is the easiest approach.

    For DC coupling, DIN+/- are tied to VCC through 50-Ohm termination. This is a typical CML input. As long as you have a CML driver with the same VCC potential as ONET4211 and output level is within 200mV to 1600mV you should be able to DC couple.

    Regards,,nasser
  • Hi Nasser,

    What you are talking about is quite clear and follows from datasheet. My question was about common mode input voltage for DIN+ and DIN- pins.
    Let me explain you our task in more detail. Today we use ONET1151LRGET laser driver for short pulse generation (duration 200 ps, repetition time 3.2 ns). As long as I understand this driver for communication purpose and we experience a lot of problems with it. Amplitude of laser pulses varies with time, if duration of input electric pulses changes than duration of laser pulse does not change equivalently. My guess is to use DC coupling with ONET4211LD because of huge ones and zeros disbalance. We use FPGA's Gigabit Transceiver for sequence of pulses generation. It has differential CML outputs with 800mV common mode voltage range and variable differential output voltage swing from 200mV to 1000mV. Is it going to work with ONET4211LD laser driver? That is not clear from documentation.
    Our future task is more challenging because we need to generate random sequence of pulses with constant duration and random repetition rate.
    Regards,
    Michael.
  • Hi Michael,

    Thanks for clarification.

    Given minimum and maximum ONET4211 differential input are 200mV and 1600mV, this means single ended peak to peak level is 100mV and 800mV. Also, since input is referenced to VCC through 50-ohm, this means valid common mode voltage is between Vcc-400mV and Vcc-50mV range before we run into headroom issue. However, your FPGA has 800mV common mode voltage so i think we could do one of the two below approaches:
    1). Use an active device to shift common mode voltage
    2). Or use a very large AC coupling cap such that RC time constant is higher than low frequency content of your pulse stream.

    Please let us know how this sounds.

    Regards,,nasser
  • Hi Nasser!

    The information you have provided is important for us. The use of very large AC coupling cap is not good as it sounds because there are a few disadvantages of this approach. First we are still unable to transmit DC part of signal, second a very large cap has bad performance on high frequency and we will have to use parallel small cap for HF. This, in turn, will cause higher reflections for HF and we will get low performance.
    I thought about active level shifter but it is hard to find a right one. I will be glad to get some advice from you on this matter.

    Regards, Michael.
  • Hi Michael,

    I looked and the only part that may meet this requirement is a device from Onsemi part number: NB6L72M. This is a 2X2 cross point but you can set termination voltage on input and output could be CML referenced to 3.3V.

    Regards,,nasser
  • Hi Naseer,

    Thank you very much.

    Regards,Michael