This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB948-Q1: OUTPUT_SLEEP_STATE_SELECT problem

Part Number: DS90UB948-Q1

Hello TI Experts,

I come here again~

        When I am using DS90UB948, No matter I  config "OUTPUT_SLEEP_STATE_SELECT" to 1 or 0, their is normal output in LOCK and vide0.

        But according to table2 in 948's datasheet, when OUTPUT_SLEEP_STATE_SELECT is set to 0,  their will be no outout in lock and video~

Why?It's strange~

     according to the datasheet,when lock is reset, I need to register OSSS(output sleep state select) higa,and then lock will be high~

but when I test,we don't have to set OSSS to 1,when it's set to 0, Lock will also have normal output~

Another question,

When host → 947 → 948 → MCU all work well,then I turn off host's LVDS output, 948's LOCK status doesn's change,it's still high~

So when their is an abnormal situation,I cann't figure out if it's caused by 947 or 948~

By the way, if 0x0c register of 948 and LOCK IO are always the same status?

\

  • 1. Please follow up the d/s, if you think output sleep state selection has problem, I would suggest you dump up the reg. of UB948 and check whether the setting is correct or not. also, LOCK/Data are low if 0x02 is set correctly.
    2. When UB947's LVDS is lost, the link between UB947 and UB948 also can work. you can send out the GPIO to notify the panel side that the signal is lost. also, you can check the reg. 0x1B, the link freq. would be changed due to diff. signal source.
    3. yes.

    regards,
    Steven
  • Hello Steven,

    Thank you very much for your quickly respond~

    I have checked the 0x02 register,when the value of 0x02 is 90(1001 0000) or 80(1000 0000),lock status is always high~it's really strange cause it's different from TABLE2 in 948's datasheet~

    You can refer to the register below   PS:0X18 is for watchdog,so it has changed ~

    20180814_162050_normal_OSSS=1.txt
    00: 68
    01: 04
    02: 90
    03: f0
    04: fe
    05: 1e
    06: 00
    07: 34
    08: 00
    09: 00
    0a: 00
    0b: 00
    0c: 00
    0d: 00
    0e: 00
    0f: 00
    10: 00
    11: 00
    12: 00
    13: 00
    14: 00
    15: 00
    16: 00
    17: 00
    18: 34
    19: 01
    1a: 00
    1b: 00
    1c: 33
    1d: 1d
    1e: 0b
    1f: 00
    20: 00
    21: 00
    22: 40
    23: 20
    24: 08
    25: 00
    26: 83
    27: 84
    28: 11
    29: 00
    2a: 00
    2b: 00
    2c: 00
    2d: 00
    2e: 00
    2f: 00
    30: 00
    31: 00
    32: 90
    33: 25
    34: 09
    35: 00
    36: 00
    37: 88
    38: 00
    39: 00
    3a: 00
    3b: 05
    3c: 20
    3d: e0
    3e: 23
    3f: 00
    40: 43
    41: 03
    42: 03
    43: 00
    44: 60
    45: 88
    46: 00
    47: 00
    48: 0f
    49: 00
    4a: 00
    4b: 08
    4c: 00
    4d: 00
    4e: 63
    4f: 00
    50: 03
    51: 10
    52: 00
    53: 01
    54: 80
    55: 00
    56: 00
    57: 00
    58: 00
    59: 7f
    5a: 20
    5b: 20
    5c: 00
    5d: 00
    5e: 00
    5f: 00
    60: 00
    61: 00
    62: 00
    63: 00
    64: 10
    65: 00
    66: 18
    67: 0f
    68: 00
    69: 00
    6a: 00
    6b: 00
    6c: 00
    6d: 00
    6e: 02
    6f: 00
    70: 00
    71: 00
    72: 00
    73: 07
    74: 07
    75: 08
    76: 00
    77: 00
    78: 00
    79: 00
    7a: 00
    7b: 00
    7c: 02
    7d: 00
    7e: 00
    7f: 00
    80: 00
    81: 00
    82: 00
    83: 00
    84: 00
    85: 00
    86: 00
    87: 00
    88: 00
    89: 00
    8a: 00
    8b: 00
    8c: 00
    8d: 00
    8e: 00
    8f: 00
    90: 00
    91: 00
    92: 00
    93: 00
    94: 00
    95: 00
    96: 00
    97: 00
    98: 00
    99: 00
    9a: 00
    9b: 00
    9c: 00
    9d: 00
    9e: 00
    9f: 00
    a0: 00
    a1: 00
    a2: 7d
    a3: 00
    a4: 00
    a5: 00
    a6: 00
    a7: 00
    a8: 00
    a9: 00
    aa: 00
    ab: 00
    ac: 00
    ad: 00
    ae: 00
    af: 00
    b0: 00
    b1: 00
    b2: 00
    b3: 00
    b4: 00
    b5: 00
    b6: 00
    b7: 00
    b8: 00
    b9: 00
    ba: 00
    bb: 00
    bc: 00
    bd: 00
    be: 00
    bf: 00
    c0: 00
    c1: 00
    c2: 00
    c3: 00
    c4: 00
    c5: 00
    c6: 00
    c7: 00
    c8: c0
    c9: 00
    ca: 00
    cb: 00
    cc: 00
    cd: 00
    ce: 00
    cf: 00
    d0: 00
    d1: 00
    d2: 00
    d3: 00
    d4: 00
    d5: 00
    d6: 00
    d7: 00
    d8: 00
    d9: 00
    da: 00
    db: 00
    dc: 00
    dd: 00
    de: 00
    df: 00
    e0: 00
    e1: 00
    e2: 00
    e3: 00
    e4: 00
    e5: 00
    e6: 00
    e7: 00
    e8: 00
    e9: 00
    ea: 00
    eb: 00
    ec: 00
    ed: 00
    ee: 00
    ef: 00
    f0: 5f
    f1: 55
    f2: 42
    f3: 39
    f4: 34
    f5: 38
    

    20180814_162727_normal OSSS=0.txt
    00: 68
    01: 04
    02: 80
    03: f0
    04: fe
    05: 1e
    06: 00
    07: 34
    08: 00
    09: 00
    0a: 00
    0b: 00
    0c: 00
    0d: 00
    0e: 00
    0f: 00
    10: 00
    11: 00
    12: 00
    13: 00
    14: 00
    15: 00
    16: 00
    17: 00
    18: fa
    19: 01
    1a: 00
    1b: 00
    1c: 33
    1d: 1d
    1e: 0b
    1f: 00
    20: 00
    21: 00
    22: 40
    23: 20
    24: 08
    25: 00
    26: 83
    27: 84
    28: 11
    29: 00
    2a: 00
    2b: 00
    2c: 00
    2d: 00
    2e: 00
    2f: 00
    30: 00
    31: 00
    32: 90
    33: 25
    34: 09
    35: 00
    36: 00
    37: 88
    38: 00
    39: 00
    3a: 00
    3b: 05
    3c: 20
    3d: e0
    3e: 23
    3f: 00
    40: 43
    41: 03
    42: 03
    43: 00
    44: 60
    45: 88
    46: 00
    47: 00
    48: 0f
    49: 00
    4a: 00
    4b: 08
    4c: 00
    4d: 00
    4e: 63
    4f: 00
    50: 03
    51: 10
    52: 00
    53: 01
    54: 80
    55: 00
    56: 00
    57: 00
    58: 00
    59: 7f
    5a: 20
    5b: 20
    5c: 00
    5d: 00
    5e: 00
    5f: 00
    60: 00
    61: 00
    62: 00
    63: 00
    64: 10
    65: 00
    66: 18
    67: 0f
    68: 00
    69: 00
    6a: 00
    6b: 00
    6c: 00
    6d: 00
    6e: 02
    6f: 00
    70: 00
    71: 00
    72: 00
    73: 07
    74: 07
    75: 08
    76: 00
    77: 00
    78: 00
    79: 00
    7a: 00
    7b: 00
    7c: 02
    7d: 00
    7e: 00
    7f: 00
    80: 00
    81: 00
    82: 00
    83: 00
    84: 00
    85: 00
    86: 00
    87: 00
    88: 00
    89: 00
    8a: 00
    8b: 00
    8c: 00
    8d: 00
    8e: 00
    8f: 00
    90: 00
    91: 00
    92: 00
    93: 00
    94: 00
    95: 00
    96: 00
    97: 00
    98: 00
    99: 00
    9a: 00
    9b: 00
    9c: 00
    9d: 00
    9e: 00
    9f: 00
    a0: 00
    a1: 00
    a2: 7d
    a3: 00
    a4: 00
    a5: 00
    a6: 00
    a7: 00
    a8: 00
    a9: 00
    aa: 00
    ab: 00
    ac: 00
    ad: 00
    ae: 00
    af: 00
    b0: 00
    b1: 00
    b2: 00
    b3: 00
    b4: 00
    b5: 00
    b6: 00
    b7: 00
    b8: 00
    b9: 00
    ba: 00
    bb: 00
    bc: 00
    bd: 00
    be: 00
    bf: 00
    c0: 00
    c1: 00
    c2: 00
    c3: 00
    c4: 00
    c5: 00
    c6: 00
    c7: 00
    c8: c0
    c9: 00
    ca: 00
    cb: 00
    cc: 00
    cd: 00
    ce: 00
    cf: 00
    d0: 00
    d1: 00
    d2: 00
    d3: 00
    d4: 00
    d5: 00
    d6: 00
    d7: 00
    d8: 00
    d9: 00
    da: 00
    db: 00
    dc: 00
    dd: 00
    de: 00
    df: 00
    e0: 00
    e1: 00
    e2: 00
    e3: 00
    e4: 00
    e5: 00
    e6: 00
    e7: 00
    e8: 00
    e9: 00
    ea: 00
    eb: 00
    ec: 00
    ed: 00
    ee: 00
    ef: 00
    f0: 5f
    f1: 55
    f2: 42
    f3: 39
    f4: 34
    f5: 38
    

  • When ub947's LVDS lost, the frequency changed to 70MHz from 74MHz,lock is high~~~Then I set 947's PDB,the frequency becomes to 0, their is no lock output~
  • pls read d/s page50, to use reg. setting of OSSS, you should set the OUTPUT ENABLE OVERRIDE firstly. so the setting in your case is not right.

    regards,
    Steven
  • T^T, I change the 0x02 register to D0(1101 0000) and lock status is still high~

    I am  confused of the register 0x02,what's the relationship of bit 4/6/7 ?



    In addition, LOCK means "Verify link established between SER and DES "
    When ub947's LVDS lost, the frequency changed to 70MHz from 74MHz,lock is high~~~Then I set 947's PDB,the frequency becomes to 0, their is no lock output~
    Is it strange? after set PDB, lock becomes low~

  • To set 0x02[7] and 0x02[4], the 0x02[6] should be set b'1!!! for this case, the setting is 0xd0, the OE and OSS is "high", please check the output status in table2 dependent on "serial input" and PDB status.
    if you set 0x02=0x50, the Lock should be "low" based on table2.

    regards,
    Steven
  • but I set 0x02=0x50 the Lock  is  still "high"

    20180816_181840_normal.txt
    00: 68
    01: 04
    02: 50
    03: f0
    04: fe
    05: 1e
    06: 00
    07: 34
    08: 00
    09: 00
    0a: 00
    0b: 00
    0c: 00
    0d: 00
    0e: 00
    0f: 00
    10: 00
    11: 00
    12: 00
    13: 00
    14: 00
    15: 00
    16: 00
    17: 00
    18: 89
    19: 01
    1a: 00
    1b: 00
    1c: 33
    1d: 1d
    1e: 09
    1f: 00
    20: 00
    21: 00
    22: 00
    23: 20
    24: 08
    25: 00
    26: 83
    27: 84
    28: 11
    29: 00
    2a: 00
    2b: 00
    2c: 00
    2d: 00
    2e: 00
    2f: 00
    30: 00
    31: 00
    32: 90
    33: 25
    34: 09
    35: 00
    36: 00
    37: 88
    38: 00
    39: 00
    3a: 00
    3b: 0f
    3c: 20
    3d: e0
    3e: 23
    3f: 00
    40: 43
    41: 03
    42: 03
    43: 00
    44: 60
    45: 88
    46: 00
    47: 00
    48: 0f
    49: 00
    4a: 00
    4b: 08
    4c: 00
    4d: 00
    4e: 63
    4f: 00
    50: 03
    51: 10
    52: 00
    53: 01
    54: 80
    55: 00
    56: 00
    57: 00
    58: 00
    59: 7f
    5a: 20
    5b: 20
    5c: 00
    5d: 00
    5e: 00
    5f: 00
    60: 00
    61: 00
    62: 00
    63: 00
    64: 10
    65: 00
    66: 18
    67: 0f
    68: 00
    69: 00
    6a: 00
    6b: 00
    6c: 00
    6d: 00
    6e: 00
    6f: 00
    70: 00
    71: 00
    72: 00
    73: 07
    74: 07
    75: 08
    76: 00
    77: 00
    78: 00
    79: 00
    7a: 00
    7b: 00
    7c: 02
    7d: 00
    7e: 00
    7f: 00
    80: 00
    81: 00
    82: 00
    83: 00
    84: 00
    85: 00
    86: 00
    87: 00
    88: 00
    89: 00
    8a: 00
    8b: 00
    8c: 00
    8d: 00
    8e: 00
    8f: 00
    90: 00
    91: 00
    92: 00
    93: 00
    94: 00
    95: 00
    96: 00
    97: 00
    98: 00
    99: 00
    9a: 00
    9b: 00
    9c: 00
    9d: 00
    9e: 00
    9f: 00
    a0: 00
    a1: 00
    a2: 7d
    a3: 00
    a4: 00
    a5: 00
    a6: 00
    a7: 00
    a8: 00
    a9: 00
    aa: 00
    ab: 00
    ac: 00
    ad: 00
    ae: 00
    af: 00
    b0: 00
    b1: 00
    b2: 00
    b3: 00
    b4: 00
    b5: 00
    b6: 00
    b7: 00
    b8: 00
    b9: 00
    ba: 00
    bb: 00
    bc: 00
    bd: 00
    be: 00
    bf: 00
    c0: 00
    c1: 00
    c2: 00
    c3: 00
    c4: 00
    c5: 00
    c6: 00
    c7: 00
    c8: c0
    c9: 00
    ca: 00
    cb: 00
    cc: 00
    cd: 00
    ce: 00
    cf: 00
    d0: 00
    d1: 00
    d2: 00
    d3: 00
    d4: 00
    d5: 00
    d6: 00
    d7: 00
    d8: 00
    d9: 00
    da: 00
    db: 00
    dc: 00
    dd: 00
    de: 00
    df: 00
    e0: 00
    e1: 00
    e2: 00
    e3: 00
    e4: 00
    e5: 00
    e6: 00
    e7: 00
    e8: 00
    e9: 00
    ea: 00
    eb: 00
    ec: 00
    ed: 00
    ee: 00
    ef: 00
    f0: 5f
    f1: 55
    f2: 42
    f3: 39
    f4: 34
    f5: 38
    

  • The lock is pull-up or not?

  • Hello Steven,

    The 948's lock pin is connected a 0Ω resistance  and then connected to MCU~

  • Pls isolate the MCU issue by removing this 0ohms resistor, and try the diff. setting providing in the reg. to set the OSSS/OEN of UB948.

    Steven

  • "When ub947's LVDS lost, the frequency changed to 70MHz from 74MHz,lock is high~~~Then I set 947's PDB,the frequency becomes to 0, their is no lock output."
    "after set PDB, lock becomes low~"
    how can 947 detect LVDS clock lost, before reset 947 by PDB?
    I tried setting reg 0x03[1]PCLK Auto to 0, it does not work.
  • sorry, what is your question here? if lvds clock is lost, ub947 will work with internal clock.

    Steven