We are validating USB2.0 feature of USB3.0 IP using TUSB1310A transceiver . At start up, observed that Link controller is writing reset in functional control register (value in data bus : Reg write - 0x84 and Value - 0x75 ) throug ulpi interface. During this PHY is asserted ulpi_nxt signal . After Controller asserts STP, we could not see PHY is asserting Ulpi_Dir High. Why? Also we would like to know how many clock cycles PHY will take to assert ULPI Dir High ?