Other Parts Discussed in Thread: TUSB8042,
Hi Team,
I finish second layout based on TI feedback from this link: e2e.ti.com/.../2551921
Please check my schematic.
Thanks,
Shlomi
diff_nets_lenght.txt
LISTING: 30 element(s)
Item 1 < NET >
Net Name: N16479540
Member of Diff Pair: DP_N16479533
Pin count: 2
Via count: 2
Total etch length: 4312.41 MIL
Total manhattan length: 2526.55 MIL
Percent manhattan: 170.68%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U1.22 BI CDSDefaultIO_2p5v (3394.52 2052.03)
R120.2 UNSPEC (1005.00 1915.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):n16479540
ELECTRICAL_CONSTRAINT_SET = 100OHM-L3
DIFFP_UNCOUPLED_LENGTH = 421 MIL
Electrical Constraints assigned to net N16479540
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 421 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U1.22 to R120.2 min= 4302.73 MIL max= 4312.73 MIL actual= 4303.29 MIL
DPData: gap=10.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 421.00
(3394.52,2052.03) pin U1.22,BI,TOP/TOP
112.12 MIL cline TOP
(3406.81,1945.00) via TOP/BOTTOM
2129.43 MIL cline L3
(2315.20,895.00) db_t
9.04 MIL cline L3
(2307.67,900.00) db_t
1948.38 MIL cline L3
(1002.13,2018.13) via TOP/BOTTOM
104.32 MIL cline TOP
(1005.00,1915.00) pin R120.2,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP_N16479533
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 2 < NET >
Net Name: N16479533
Member of Diff Pair: DP_N16479533
Pin count: 2
Via count: 2
Total etch length: 4307.73 MIL
Total manhattan length: 2556.87 MIL
Percent manhattan: 168.48%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U1.21 BI CDSDefaultIO_2p5v (3374.84 2052.03)
R119.2 UNSPEC (955.00 1915.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):n16479533
ELECTRICAL_CONSTRAINT_SET = 100OHM-L3
DIFFP_UNCOUPLED_LENGTH = 421 MIL
Electrical Constraints assigned to net N16479533
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 421 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U1.21 to R119.2 min= 4298.29 MIL max= 4308.29 MIL actual= 4307.73 MIL
DPData: gap=10.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 421.00
(3374.84,2052.03) pin U1.21,BI,TOP/TOP
112.12 MIL cline TOP
(3362.56,1945.00) via TOP/BOTTOM
4063.03 MIL cline L3
(957.88,2018.13) via TOP/BOTTOM
132.59 MIL cline TOP
(955.00,1915.00) pin R119.2,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP_N16479533
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 3 < NET >
Net Name: USB_DM_DN1
Member of Diff Pair: DP1
Pin count: 3
Via count: 0
Total etch length: 2083.47 MIL
Total manhattan length: 1306.71 MIL
Percent manhattan: 159.44%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.2 BI CDSDefaultIO_2p5v (1148.20 1502.08)
DN1.2 UNSPEC (1490.63 759.25)
J11.2 UNSPEC (1488.43 540.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dm_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DM_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.2 to J11.2 min= 2076.13 MIL max= 2086.13 MIL actual= 2083.47 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1148.20,1502.08) pin U11.2,BI,TOP/TOP
937.3 MIL cline TOP
(1490.63,759.25) pin DN1.2,UNSPEC,TOP/TOP
1146.17 MIL cline TOP
(1488.43,540.00) pin J11.2,UNSPEC,TOP/BOTTOM
Member of Groups:
DIFF_PAIR : DP1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 4 < NET >
Net Name: USB_DP_DN1
Member of Diff Pair: DP1
Pin count: 3
Via count: 0
Total etch length: 2081.13 MIL
Total manhattan length: 1361.37 MIL
Percent manhattan: 152.87%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.1 BI CDSDefaultIO_2p5v (1148.20 1482.40)
DN1.1 UNSPEC (1474.88 761.22)
J11.3 UNSPEC (1567.17 540.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dp_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DP_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.1 to J11.3 min= 2078.47 MIL max= 2088.47 MIL actual= 2081.13 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1148.20,1482.40) pin U11.1,BI,TOP/TOP
910.52 MIL cline TOP
(1474.88,761.22) pin DN1.1,UNSPEC,TOP/TOP
1170.6 MIL cline TOP
(1567.17,540.00) pin J11.3,UNSPEC,TOP/BOTTOM
Member of Groups:
DIFF_PAIR : DP1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 5 < NET >
Net Name: CAP_SSTXM_DN1
Member of Diff Pair: DP1_CAP
Pin count: 3
Via count: 0
Total etch length: 1203.86 MIL
Total manhattan length: 1363.17 MIL
Percent manhattan: 88.31%
Pin Type SigNoise Model Location
--- ---- -------------- --------
C72.2 UNSPEC (1204.45 1540.00)
DN1.5 UNSPEC (1537.87 759.25)
J11.8 UNSPEC (1449.06 599.06)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):cap_sstxm_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net CAP_SSTXM_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) C72.2 to J11.8 min= 1197.7 MIL max= 1207.7 MIL actual= 1203.86 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1204.45,1540.00) pin C72.2,UNSPEC,TOP/TOP
979.47 MIL cline TOP
(1537.87,759.25) pin DN1.5,UNSPEC,TOP/TOP
224.4 MIL cline TOP
(1449.06,599.06) pin J11.8,UNSPEC,TOP/BOTTOM
Member of Groups:
DIFF_PAIR : DP1_CAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 6 < NET >
Net Name: CAP_SSTXP_DN1
Member of Diff Pair: DP1_CAP
Pin count: 3
Via count: 0
Total etch length: 1202.7 MIL
Total manhattan length: 1390.44 MIL
Percent manhattan: 86.50%
Pin Type SigNoise Model Location
--- ---- -------------- --------
C73.2 UNSPEC (1204.45 1520.00)
DN1.4 UNSPEC (1522.13 759.25)
J11.9 UNSPEC (1370.31 599.06)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):cap_sstxp_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net CAP_SSTXP_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J11.9 to C73.2 min= 1198.86 MIL max= 1208.86 MIL actual= 1202.7 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1370.31,599.06) pin J11.9,UNSPEC,TOP/BOTTOM
263.35 MIL cline TOP
(1522.13,759.25) pin DN1.4,UNSPEC,TOP/TOP
939.36 MIL cline TOP
(1204.45,1520.00) pin C73.2,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP1_CAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 7 < NET >
Net Name: USB_SSRXP_DN1
Member of Diff Pair: DP1_RX
Pin count: 3
Via count: 0
Total etch length: 1336.95 MIL
Total manhattan length: 1440.08 MIL
Percent manhattan: 92.84%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.6 IN CDSDefaultInput_2p5v (1148.20 1580.80)
DN1.7 UNSPEC (1569.37 759.25)
J11.6 UNSPEC (1606.54 599.06)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_ssrxp_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSRXP_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) DN1.7 to U11.6 min= 1127.62 MIL max= 1137.62 MIL actual= 1135.27 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1569.37,759.25) pin DN1.7,UNSPEC,TOP/TOP
1135.27 MIL cline TOP
(1148.20,1580.80) pin U11.6,IN,TOP/TOP
(SPhase) DN1.7 to J11.6 min= 196.68 MIL max= 206.68 MIL actual= 201.68 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1569.37,759.25) pin DN1.7,UNSPEC,TOP/TOP
201.68 MIL cline TOP
(1606.54,599.06) pin J11.6,UNSPEC,TOP/BOTTOM
(SPhase) J11.6 to U11.6 min= 1329.29 MIL max= 1339.29 MIL actual= 1336.95 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1606.54,599.06) pin J11.6,UNSPEC,TOP/BOTTOM
201.68 MIL cline TOP
(1569.37,759.25) pin DN1.7,UNSPEC,TOP/TOP
1135.27 MIL cline TOP
(1148.20,1580.80) pin U11.6,IN,TOP/TOP
Member of Groups:
DIFF_PAIR : DP1_RX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 8 < NET >
Net Name: USB_SSRXM_DN1
Member of Diff Pair: DP1_RX
Pin count: 3
Via count: 0
Total etch length: 1334.29 MIL
Total manhattan length: 1538.5 MIL
Percent manhattan: 86.73%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.7 IN CDSDefaultInput_2p5v (1148.20 1600.48)
DN1.8 UNSPEC (1585.12 759.25)
J11.5 UNSPEC (1685.28 599.06)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_ssrxm_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSRXM_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) DN1.8 to U11.7 min= 1130.27 MIL max= 1140.27 MIL actual= 1132.62 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1585.12,759.25) pin DN1.8,UNSPEC,TOP/TOP
1132.62 MIL cline TOP
(1148.20,1600.48) pin U11.7,IN,TOP/TOP
(SPhase) DN1.8 to J11.5 min= 196.68 MIL max= 206.68 MIL actual= 201.68 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1585.12,759.25) pin DN1.8,UNSPEC,TOP/TOP
201.68 MIL cline TOP
(1685.28,599.06) pin J11.5,UNSPEC,TOP/BOTTOM
(SPhase) J11.5 to U11.7 min= 1331.95 MIL max= 1341.95 MIL actual= 1334.29 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1685.28,599.06) pin J11.5,UNSPEC,TOP/BOTTOM
201.68 MIL cline TOP
(1585.12,759.25) pin DN1.8,UNSPEC,TOP/TOP
1132.62 MIL cline TOP
(1148.20,1600.48) pin U11.7,IN,TOP/TOP
Member of Groups:
DIFF_PAIR : DP1_RX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 9 < NET >
Net Name: USB_SSTXP_DN1
Member of Diff Pair: DP1_TX
Pin count: 2
Via count: 0
Total etch length: 38.08 MIL
Total manhattan length: 39.11 MIL
Percent manhattan: 97.36%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.3 OUT CDSDefaultOutput_2p5v (1148.20 1521.76)
C73.1 UNSPEC (1185.55 1520.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_sstxp_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSTXP_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.3 to C73.1 min= 34.8 MIL max= 44.8 MIL actual= 38.08 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1148.20,1521.76) pin U11.3,OUT,TOP/TOP
38.08 MIL cline TOP
(1185.55,1520.00) pin C73.1,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP1_TX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 10 < NET >
Net Name: USB_SSTXM_DN1
Member of Diff Pair: DP1_TX
Pin count: 2
Via count: 0
Total etch length: 39.8 MIL
Total manhattan length: 38.79 MIL
Percent manhattan: 102.61%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.4 OUT CDSDefaultOutput_2p5v (1148.20 1541.44)
C72.1 UNSPEC (1185.55 1540.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_sstxm_dn1
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSTXM_DN1
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.4 to C72.1 min= 33.08 MIL max= 43.08 MIL actual= 39.8 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1148.20,1541.44) pin U11.4,OUT,TOP/TOP
39.8 MIL cline TOP
(1185.55,1540.00) pin C72.1,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP1_TX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 11 < NET >
Net Name: USB_DM_DN4
Member of Diff Pair: DP2
Pin count: 2
Via count: 0
Total etch length: 56.01 MIL
Total manhattan length: 61.96 MIL
Percent manhattan: 90.39%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.25 BI CDSDefaultIO_2p5v (965.16 1803.20)
R119.1 UNSPEC (955.00 1855.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dm_dn4
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DM_DN4
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) R119.1 to U11.25 min= 55.15 MIL max= 65.15 MIL actual= 56.01 MIL
DPData: gap=10.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(955.00,1855.00) pin R119.1,UNSPEC,TOP/TOP
56.01 MIL cline TOP
(965.16,1803.20) pin U11.25,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 12 < NET >
Net Name: USB_DP_DN4
Member of Diff Pair: DP2
Pin count: 2
Via count: 0
Total etch length: 60.15 MIL
Total manhattan length: 71.96 MIL
Percent manhattan: 83.59%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.24 BI CDSDefaultIO_2p5v (984.84 1803.20)
R120.1 UNSPEC (1005.00 1855.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dp_dn4
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DP_DN4
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) R120.1 to U11.24 min= 51.01 MIL max= 61.01 MIL actual= 60.15 MIL
DPData: gap=10.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1005.00,1855.00) pin R120.1,UNSPEC,TOP/TOP
60.15 MIL cline TOP
(984.84,1803.20) pin U11.24,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 13 < NET >
Net Name: CAP_SSTXM_DN2
Member of Diff Pair: DP2_CAP
Pin count: 3
Via count: 0
Total etch length: 2063.15 MIL
Total manhattan length: 2117.43 MIL
Percent manhattan: 97.44%
Pin Type SigNoise Model Location
--- ---- -------------- --------
C80.2 UNSPEC (1204.45 1700.00)
DN2.5 UNSPEC (1447.13 3305.75)
J12.8 UNSPEC (1535.94 3485.94)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):cap_sstxm_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net CAP_SSTXM_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) C80.2 to J12.8 min= 2059.84 MIL max= 2069.84 MIL actual= 2063.15 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1204.45,1700.00) pin C80.2,UNSPEC,TOP/TOP
1839.25 MIL cline TOP
(1447.13,3305.75) pin DN2.5,UNSPEC,TOP/TOP
223.9 MIL cline TOP
(1535.94,3485.94) pin J12.8,UNSPEC,TOP/BOTTOM
Member of Groups:
DIFF_PAIR : DP2_CAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 14 < NET >
Net Name: CAP_SSTXP_DN2
Member of Diff Pair: DP2_CAP
Pin count: 3
Via count: 0
Total etch length: 2064.84 MIL
Total manhattan length: 2221.18 MIL
Percent manhattan: 92.96%
Pin Type SigNoise Model Location
--- ---- -------------- --------
C81.2 UNSPEC (1204.45 1675.00)
DN2.4 UNSPEC (1462.87 3305.75)
J12.9 UNSPEC (1614.69 3485.94)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):cap_sstxp_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net CAP_SSTXP_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J12.9 to C81.2 min= 2058.15 MIL max= 2068.15 MIL actual= 2064.84 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1614.69,3485.94) pin J12.9,UNSPEC,TOP/BOTTOM
262.85 MIL cline TOP
(1462.87,3305.75) pin DN2.4,UNSPEC,TOP/TOP
1801.99 MIL cline TOP
(1204.45,1675.00) pin C81.2,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_CAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 15 < NET >
Net Name: USB_DP_DN2
Member of Diff Pair: DP2_D
Pin count: 3
Via count: 0
Total etch length: 3205.14 MIL
Total manhattan length: 2359.37 MIL
Percent manhattan: 135.85%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.9 BI CDSDefaultIO_2p5v (1148.20 1639.84)
DN2.1 UNSPEC (1510.12 3303.78)
J12.3 UNSPEC (1417.83 3545.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dp_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DP_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J12.3 to U11.9 min= 3197.42 MIL max= 3207.42 MIL actual= 3205.14 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1417.83,3545.00) pin J12.3,UNSPEC,TOP/BOTTOM
1227.39 MIL cline TOP
(1510.12,3303.78) pin DN2.1,UNSPEC,TOP/TOP
1977.75 MIL cline TOP
(1148.20,1639.84) pin U11.9,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_D
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 16 < NET >
Net Name: USB_DM_DN2
Member of Diff Pair: DP2_D
Pin count: 3
Via count: 0
Total etch length: 3202.42 MIL
Total manhattan length: 2233.85 MIL
Percent manhattan: 143.36%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.10 BI CDSDefaultIO_2p5v (1148.20 1659.52)
DN2.2 UNSPEC (1494.37 3305.75)
J12.2 UNSPEC (1496.57 3545.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dm_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DM_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J12.2 to U11.10 min= 3200.14 MIL max= 3210.14 MIL actual= 3202.42 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1496.57,3545.00) pin J12.2,UNSPEC,TOP/BOTTOM
1250.88 MIL cline TOP
(1494.37,3305.75) pin DN2.2,UNSPEC,TOP/TOP
1951.54 MIL cline TOP
(1148.20,1659.52) pin U11.10,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_D
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 17 < NET >
Net Name: USB_SSRXM_DN2
Member of Diff Pair: DP2_RX
Pin count: 3
Via count: 0
Total etch length: 1929.32 MIL
Total manhattan length: 2079.86 MIL
Percent manhattan: 92.76%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.15 IN CDSDefaultInput_2p5v (1148.20 1757.92)
DN2.8 UNSPEC (1399.88 3305.75)
J12.5 UNSPEC (1299.72 3485.94)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_ssrxm_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSRXM_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) DN2.8 to U11.15 min= 1699.92 MIL max= 1709.92 MIL actual= 1707.64 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1399.88,3305.75) pin DN2.8,UNSPEC,TOP/TOP
1707.64 MIL cline TOP
(1148.20,1757.92) pin U11.15,IN,TOP/TOP
(SPhase) DN2.8 to J12.5 min= 216.68 MIL max= 226.68 MIL actual= 221.68 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1399.88,3305.75) pin DN2.8,UNSPEC,TOP/TOP
221.68 MIL cline TOP
(1299.72,3485.94) pin J12.5,UNSPEC,TOP/BOTTOM
(SPhase) J12.5 to U11.15 min= 1921.6 MIL max= 1931.6 MIL actual= 1929.32 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1299.72,3485.94) pin J12.5,UNSPEC,TOP/BOTTOM
221.68 MIL cline TOP
(1399.88,3305.75) pin DN2.8,UNSPEC,TOP/TOP
1707.64 MIL cline TOP
(1148.20,1757.92) pin U11.15,IN,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_RX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 18 < NET >
Net Name: USB_SSRXP_DN2
Member of Diff Pair: DP2_RX
Pin count: 3
Via count: 0
Total etch length: 1926.6 MIL
Total manhattan length: 2052.3 MIL
Percent manhattan: 93.88%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.14 IN CDSDefaultInput_2p5v (1148.20 1738.24)
DN2.7 UNSPEC (1415.63 3305.75)
J12.6 UNSPEC (1378.46 3485.94)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_ssrxp_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSRXP_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) DN2.7 to U11.14 min= 1702.64 MIL max= 1712.64 MIL actual= 1704.92 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1415.63,3305.75) pin DN2.7,UNSPEC,TOP/TOP
1704.92 MIL cline TOP
(1148.20,1738.24) pin U11.14,IN,TOP/TOP
(SPhase) DN2.7 to J12.6 min= 216.68 MIL max= 226.68 MIL actual= 221.68 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1415.63,3305.75) pin DN2.7,UNSPEC,TOP/TOP
221.68 MIL cline TOP
(1378.46,3485.94) pin J12.6,UNSPEC,TOP/BOTTOM
(SPhase) J12.6 to U11.14 min= 1924.32 MIL max= 1934.32 MIL actual= 1926.6 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1378.46,3485.94) pin J12.6,UNSPEC,TOP/BOTTOM
221.68 MIL cline TOP
(1415.63,3305.75) pin DN2.7,UNSPEC,TOP/TOP
1704.92 MIL cline TOP
(1148.20,1738.24) pin U11.14,IN,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_RX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 19 < NET >
Net Name: USB_SSTXP_DN2
Member of Diff Pair: DP2_TX
Pin count: 2
Via count: 0
Total etch length: 39.09 MIL
Total manhattan length: 41.55 MIL
Percent manhattan: 94.08%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.11 OUT CDSDefaultOutput_2p5v (1148.20 1679.20)
C81.1 UNSPEC (1185.55 1675.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_sstxp_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSTXP_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.11 to C81.1 min= 32.81 MIL max= 42.81 MIL actual= 39.09 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1148.20,1679.20) pin U11.11,OUT,TOP/TOP
39.09 MIL cline TOP
(1185.55,1675.00) pin C81.1,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_TX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 20 < NET >
Net Name: USB_SSTXM_DN2
Member of Diff Pair: DP2_TX
Pin count: 2
Via count: 0
Total etch length: 37.81 MIL
Total manhattan length: 38.47 MIL
Percent manhattan: 98.29%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.12 OUT CDSDefaultOutput_2p5v (1148.20 1698.88)
C80.1 UNSPEC (1185.55 1700.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_sstxm_dn2
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSTXM_DN2
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.12 to C80.1 min= 34.09 MIL max= 44.09 MIL actual= 37.81 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(1148.20,1698.88) pin U11.12,OUT,TOP/TOP
37.81 MIL cline TOP
(1185.55,1700.00) pin C80.1,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : DP2_TX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 21 < NET >
Net Name: USB_SSRXM_UP
Member of Diff Pair: DP3
Pin count: 3
Via count: 0
Total etch length: 1559.81 MIL
Total manhattan length: 1206.47 MIL
Percent manhattan: 129.29%
Pin Type SigNoise Model Location
--- ---- -------------- --------
J13.8 UNSPEC (558.74 715.79)
DN3.8 UNSPEC (724.25 759.88)
U11.59 IN CDSDefaultInput_2p5v (1024.20 1456.80)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):
DIFFP_PHASE_CONTROL = STATIC
Electrical Constraints assigned to net USB_SSRXM_UP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J13.8 to U11.59 min= 1555.93 MIL max= 1565.93 MIL actual= 1559.81 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(558.74,715.79) pin J13.8,UNSPEC,TOP/BOTTOM
630.18 MIL cline TOP
(724.25,759.88) pin DN3.8,UNSPEC,TOP/TOP
929.62 MIL cline TOP
(1024.20,1456.80) pin U11.59,IN,TOP/TOP
(SPhase) J13.8 to DN3.8 min= 651.96 MIL max= 661.96 MIL actual= 630.18 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(558.74,715.79) pin J13.8,UNSPEC,TOP/BOTTOM
630.18 MIL cline TOP
(724.25,759.88) pin DN3.8,UNSPEC,TOP/TOP
(SPhase) DN3.8 to U11.59 min= 898.97 MIL max= 908.97 MIL actual= 929.62 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(724.25,759.88) pin DN3.8,UNSPEC,TOP/TOP
929.62 MIL cline TOP
(1024.20,1456.80) pin U11.59,IN,TOP/TOP
Member of Groups:
DIFF_PAIR : DP3
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 22 < NET >
Net Name: USB_SSRXP_UP
Member of Diff Pair: DP3
Pin count: 3
Via count: 0
Total etch length: 1560.93 MIL
Total manhattan length: 1255.69 MIL
Percent manhattan: 124.31%
Pin Type SigNoise Model Location
--- ---- -------------- --------
J13.9 UNSPEC (558.74 646.89)
DN3.7 UNSPEC (724.25 775.63)
U11.58 IN CDSDefaultInput_2p5v (1004.52 1456.80)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):
DIFFP_PHASE_CONTROL = STATIC
Electrical Constraints assigned to net USB_SSRXP_UP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J13.9 to U11.58 min= 1554.81 MIL max= 1564.81 MIL actual= 1560.93 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(558.74,646.89) pin J13.9,UNSPEC,TOP/BOTTOM
656.96 MIL cline TOP
(724.25,775.63) pin DN3.7,UNSPEC,TOP/TOP
903.97 MIL cline TOP
(1004.52,1456.80) pin U11.58,IN,TOP/TOP
(SPhase) J13.9 to DN3.7 min= 625.18 MIL max= 635.18 MIL actual= 656.96 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(558.74,646.89) pin J13.9,UNSPEC,TOP/BOTTOM
656.96 MIL cline TOP
(724.25,775.63) pin DN3.7,UNSPEC,TOP/TOP
(SPhase) DN3.7 to U11.58 min= 924.62 MIL max= 934.62 MIL actual= 903.97 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(724.25,775.63) pin DN3.7,UNSPEC,TOP/TOP
903.97 MIL cline TOP
(1004.52,1456.80) pin U11.58,IN,TOP/TOP
Member of Groups:
DIFF_PAIR : DP3
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 23 < NET >
Net Name: N16394387
Member of Diff Pair: DP3_D
Pin count: 2
Via count: 0
Total etch length: 78.39 MIL
Total manhattan length: 97.5 MIL
Percent manhattan: 80.40%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U9.8 BI CDSDefaultIO_2p5v (3020.00 1247.50)
R58.2 UNSPEC (2985.00 1185.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):n16394387
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net N16394387
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) R58.2 to U9.8 min= 74.22 MIL max= 84.22 MIL actual= 78.39 MIL
DPData: gap=10.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(2985.00,1185.00) pin R58.2,UNSPEC,TOP/TOP
78.39 MIL cline TOP
(3020.00,1247.50) pin U9.8,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : DP3_D
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 24 < NET >
Net Name: N16395496
Member of Diff Pair: DP3_D
Pin count: 2
Via count: 0
Total etch length: 79.22 MIL
Total manhattan length: 67.18 MIL
Percent manhattan: 117.92%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U9.9 BI CDSDefaultIO_2p5v (3039.68 1247.50)
R56.2 UNSPEC (3035.00 1185.00)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):n16395496
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net N16395496
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) R56.2 to U9.9 min= 73.39 MIL max= 83.39 MIL actual= 79.22 MIL
DPData: gap=10.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(3035.00,1185.00) pin R56.2,UNSPEC,TOP/TOP
79.22 MIL cline TOP
(3039.68,1247.50) pin U9.9,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : DP3_D
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 25 < NET >
Net Name: CAP_UP_SSTXM
Member of Diff Pair: UP_CAP
Pin count: 3
Via count: 0
Total etch length: 1308.67 MIL
Total manhattan length: 1165.19 MIL
Percent manhattan: 112.31%
Pin Type SigNoise Model Location
--- ---- -------------- --------
C84.2 UNSPEC (965.00 1400.55)
DN3.5 UNSPEC (724.25 807.13)
J13.5 UNSPEC (558.74 981.54)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):cap_up_sstxm
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net CAP_UP_SSTXM
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) C84.2 to J13.5 min= 1298.69 MIL max= 1308.69 MIL actual= 1308.67 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(965.00,1400.55) pin C84.2,UNSPEC,TOP/TOP
761.95 MIL cline TOP
(724.25,807.13) pin DN3.5,UNSPEC,TOP/TOP
546.72 MIL cline TOP
(558.74,981.54) pin J13.5,UNSPEC,TOP/BOTTOM
Member of Groups:
DIFF_PAIR : UP_CAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 26 < NET >
Net Name: CAP_UP_SSTXP
Member of Diff Pair: UP_CAP
Pin count: 3
Via count: 0
Total etch length: 1303.69 MIL
Total manhattan length: 1053.71 MIL
Percent manhattan: 123.72%
Pin Type SigNoise Model Location
--- ---- -------------- --------
C85.2 UNSPEC (945.00 1400.55)
DN3.4 UNSPEC (724.25 822.87)
J13.6 UNSPEC (558.74 912.64)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):cap_up_sstxp
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net CAP_UP_SSTXP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) C85.2 to J13.6 min= 1303.67 MIL max= 1313.67 MIL actual= 1303.69 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(945.00,1400.55) pin C85.2,UNSPEC,TOP/TOP
735.73 MIL cline TOP
(724.25,822.87) pin DN3.4,UNSPEC,TOP/TOP
567.97 MIL cline TOP
(558.74,912.64) pin J13.6,UNSPEC,TOP/BOTTOM
Member of Groups:
DIFF_PAIR : UP_CAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 27 < NET >
Net Name: USB_DP_UP
Member of Diff Pair: UP_D
Pin count: 3
Via count: 0
Total etch length: 1395.85 MIL
Total manhattan length: 1057.29 MIL
Percent manhattan: 132.02%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.54 BI CDSDefaultIO_2p5v (925.80 1456.80)
DN3.2 UNSPEC (724.25 854.37)
J13.2 UNSPEC (480.00 863.43)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dp_up
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DP_UP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J13.2 to U11.54 min= 1388.66 MIL max= 1398.66 MIL actual= 1395.85 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(480.00,863.43) pin J13.2,UNSPEC,TOP/BOTTOM
669.56 MIL cline TOP
(724.25,854.37) pin DN3.2,UNSPEC,TOP/TOP
726.29 MIL cline TOP
(925.80,1456.80) pin U11.54,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : UP_D
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 28 < NET >
Net Name: USB_DM_UP
Member of Diff Pair: UP_D
Pin count: 3
Via count: 0
Total etch length: 1393.66 MIL
Total manhattan length: 1098.23 MIL
Percent manhattan: 126.90%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.53 BI CDSDefaultIO_2p5v (906.12 1456.80)
DN3.1 UNSPEC (726.22 870.12)
J13.3 UNSPEC (401.26 863.43)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):usb_dm_up
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_DM_UP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) J13.3 to U11.53 min= 1390.85 MIL max= 1400.85 MIL actual= 1393.66 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(401.26,863.43) pin J13.3,UNSPEC,TOP/BOTTOM
695.24 MIL cline TOP
(726.22,870.12) pin DN3.1,UNSPEC,TOP/TOP
698.43 MIL cline TOP
(906.12,1456.80) pin U11.53,BI,TOP/TOP
Member of Groups:
DIFF_PAIR : UP_D
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 29 < NET >
Net Name: USB_SSTXM_UP
Member of Diff Pair: UP_TX
Pin count: 2
Via count: 0
Total etch length: 37.42 MIL
Total manhattan length: 37.51 MIL
Percent manhattan: 99.75%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.56 OUT CDSDefaultOutput_2p5v (965.16 1456.80)
C84.1 UNSPEC (965.00 1419.45)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSTXM_UP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.56 to C84.1 min= 32.55 MIL max= 42.55 MIL actual= 37.42 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(965.16,1456.80) pin U11.56,OUT,TOP/TOP
37.42 MIL cline TOP
(965.00,1419.45) pin C84.1,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : UP_TX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Item 30 < NET >
Net Name: USB_SSTXP_UP
Member of Diff Pair: UP_TX
Pin count: 2
Via count: 0
Total etch length: 37.55 MIL
Total manhattan length: 37.83 MIL
Percent manhattan: 99.26%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U11.55 OUT CDSDefaultOutput_2p5v (945.48 1456.80)
C85.1 UNSPEC (945.00 1419.45)
No connections remaining
Properties attached to net
LOGICAL_PATH = @dragontail2_3.root(sch_1):
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net USB_SSTXP_UP
diff pair positive coupled tolerance: 0.01 MIL
diff pair min line spacing: 5 MIL
diff pair max uncoupled length: 400 MIL
static diff pair phase tolerance: 5 mil
Constraint information:
(SPhase) U11.55 to C85.1 min= 32.42 MIL max= 42.42 MIL actual= 37.55 MIL
DPData: gap=8.00 (-0,+0.01) tolerance= 5.00; max uncoupled= 400.00
(945.48,1456.80) pin U11.55,OUT,TOP/TOP
37.55 MIL cline TOP
(945.00,1419.45) pin C85.1,UNSPEC,TOP/TOP
Member of Groups:
DIFF_PAIR : UP_TX
~ ~ ~ ~ ~ ~ ~end-of-file~ ~ ~ ~ ~ ~ ~
