This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISO6721: Power up sequence of VCC and INx, FailSafe

Part Number: ISO6721
Other Parts Discussed in Thread: SN74LVC1G17

Does ISO6721 has failsafe output, in the situation of with VCC1=0V, INA=5V?

In my customer's current design, they comes into such an situation, when system powers up, the signal for INX will rise to 5V first and VCC is still 0V.

Is there any requirements for the power up sequence?

If VCC reaches 5V firstly and then INX rises to 5V secondly is required to let ISO6721 work properly.

  • Hi Marsh,

    Thank you for reaching out.

    ISO6721 doesn't have any specific power sequencing requirements but the device does have a restriction that input signals cannot be applied without device being powered. This has been stated in the absolute maximum ratings of device input pins, please refer to the image below. As stated in the image below, the voltage at INx pins cannot be more than VCC voltage by 0.5V. i.e., if VCC = 0V then INx should be <0.5V. Violating this requirement will lead to device damage. 


    I understand that customer application requires the inputs to accept voltage even when device is not powered. This can be addressed by using a buffer that has failsafe input feature like SN74LVC1G17 which will not be damaged when input voltage is applied even when VCC is 0V. Let me know if you have any questions, thanks.


    Regards,
    Koteshwar Rao