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ISO7420FE: Output power down behavior

Eric Stoll
Prodigy 20 points
Part Number: ISO7420FE
Other Parts Discussed in Thread: ISO7420

The datasheet for the ISO7420FE specifies operation of both the input and output down to 3V.  Assuming the input side is powered to 5V with a logic low on the input.  Is it possible that the output could glitch high during power down of the output VCC2?  If so, at what level of VCC2 could a glitch occur.  If glitches can occur, are there any recommendations to mitigate this such as a pull down resistor on the output.

Stated differently, is there any POR type function on VCC2 such that the outputs of the ISO7420FE will be guaranteed to be in a logic low state during VCC2 power down with VCC1 powered.  I am looking for additional insight into what is noted in Table 2 of section 8.4 of the device datasheet.

  • +1
    TI__Genius 17100 points

    Hi Eric,

    Thank you for posting, and welcome to E2E! The POR for ISO7420 detects when voltage is below its ~3V threshold, and the corresponding outputs become high-impedance (Hi-Z) instead of HIGH or LOW.

    When local power is not present on the output power supply, a pull-down resistor can be connected to the output pin to ensure a LOW state while the pin is Hi-Z. To ensure the pull-down resistance is high enough that the isolator can source enough current for it in HIGH states, we recommend a value like 4.7kΩ.

    Please let us know if you have any additional questions.


    Respectfully,
    Manuel Chavez