Hello,
I would like to understand what copper isolation i need to have between pad to pad. The spec say that i can have 5KV isolation, but if i use the calculator: https://www.smps.us/pcbtracespacing.html with 5000V, it give me 572mils of isolation. But the SOIC is just 289mils and i don't understand why?
Can you help me to understand
Hi Amaury,
Thank you for posting, and welcome to E2E! For our devices, >8mm of creepage and clearance are needed to achieve the 5kVrms isolation performance we specify. The HV landing pattern for this device, shown below and in Section 14 of its datasheet, maintains that distance:
This 5kV isolation rating is certified by UL 1577, and it looks like the calculator tool you linked to specifies distances per IEC/UL 60950-1. This is a different standard for insultation. Our device is certified for 800V reinforced by this standard, as shown in the certifications section (copied below), which means that it provides double the creepage and clearance distance (8mm) required for working voltage levels of 800V (4mm).
I hope this answers your question. Please let us know if there is any additional assistance we can provide.
Respectfully,
Manuel Chavez
