• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 14 subscribers
  • Views 297 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN6505B-Q1: Requesting to provide the internal MOSFET information.

Vamsi Bankuru
Prodigy 100 points
Part Number: SN6505B-Q1
Other Parts Discussed in Thread: SN6505D-Q1

Hi TI Team,

Requesting to provide SN6505B-Q1 IC, internal MOSFET information i.e., gate charge, rise and fall time for MOSFET power loss calculation which will help in our design.


Kind regards,

Vamsi Bankuru

  • 0
    TI__Mastermind 21575 points

    Hello Vamsi,

    Thanks for reaching out. 

    1. Gate Charge 
      1. Since the gates of the output stage FETs are internal to the device this information is not made readily available. I believe the specs pertaining to D1 and D2 (Open drain output of the power MOSFETs) will be more relevant in your design. You can find details in section 6.5 (shown below).
    2. Rise and Fall times - Slew rate. 
      1. In this datasheet they are referred to as slew rate. Please see table 6.5 for more information.
      2.  
    3. Power Loss 
      1. Efficiency of the transformer driver is dependent on the transformer and overall system design. You can efficiency results in the 6.8 Typical Characteristics, SN6505B-Q1 or SN6505D-Q1 taken with one of the recommended transformers.
      2. 9.2.2 Detailed Design Procedure also has some information on transformer efficiency.

    Let me know if you have any further questions.

    Best,
    Andrew

  • 0
    Prodigy 100 points

    Hi Andrew,

    Can you please provide     SN6505B-Q1 IC, internal MOSFET information i.e., gate charge, rise and fall time as soon as possible, as it was currently unavailable.

    Kind regards,

    Vamsi Bankuru

  • 0 in reply to Vamsi Bankuru
    TI__Mastermind 21575 points

    Hello Vamsi,

    We don't have this exact information. The information provided in the datasheet is all we can provide publicly. 

    I have provided my inputs to these in the replies above. If you have questions on my responses, feel free to follow up. 

    Best,
    Andrew 

  • 0 in reply to Andrew Jackiw
    Prodigy 100 points

    Hi Andrew,

    Can you please follow up by converting this open query to my mail.

    Kind regards,

    Vamsi Bankuru

  • 0 in reply to Vamsi Bankuru
    TI__Mastermind 21575 points

    Hello Vamsi,

    I apologize for the confusion. I meant to show that I have provided the information to your questions regarding gate charge and rise and fall time in my initial reply, please review and follow up with additional questions or information here on E2E if possible. 

    I have quoted the portion of the original reply that is relevant to gate charge and rise and fall times below for convenience: 

    Andrew Jackiw said:
    • Gate Charge 
      1. Since the gates of the output stage FETs are internal to the device this information is not made readily available. I believe the specs pertaining to D1 and D2 (Open drain output of the power MOSFETs) will be more relevant in your design. You can find details in section 6.5 (shown below).
    • Rise and Fall times - Slew rate. 
      1. In this datasheet they are referred to as slew rate. Please see table 6.5 for more information.
      2.  

    Let me know your inputs.

    Best,
    Andrew