Hi,
We are using TI isolator to interface the differential clock signals from FPGA to the ADC as shown in the image.
We have the following two concerns.
1) Please let us know if the LVDS Signal specs mentioned in the image for all the three ICs are compatible with each other.
2) Vcc of ADC is 1.8V whereas Vcc of TI Isolator is 2.5V. Please let us know if this configuration can be implemented for the LVDS specs mentioned in the block diagram.