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ISO7242A: chattering problem

Part Number: ISO7242A
Other Parts Discussed in Thread: ISO7742, , ISO7242M, ISO7242C

Dear Technical Support Team,

My configuration is below. When I connect or disconnect the cable, chattering signal from connector reaches FPGA.

input connector→SN75LV4737ADB→ISO7242ADW→FPGA

So FPGA has chattering  reduction function. However sometimes FPGA misrecognize with chattering  reduction function with because chattering signal can't  pass through ISO7242  from V2(5V) to V1(3V).

■Q1

Is it possible to pass chattering signal through ISO7742 ?

Could you see attached waveform about chattering  with ISO7242 ?

ISO7242_chattering.pdf

■Q2

isolator of ADI such as ADuMxxx has refresh functions. Is seems to  pass the chattering signal through ISO7242 without change.

Does ISO7742 has a refresh function?

Best regards,

ttd

 

Best Regards,

ttd

  • Hi TTD,

    Thank you for reaching out to us and for sharing details of the issue. As stated in ISO7242A datasheet, the device does have DC refresh that periodically matches its the output to input unless the input circuit is unpowered. Could you please confirm if the power supply on input side is clean and not getting disturbed?

    A1. ISO7242A is rated for 1Mbps and any signal shorter than 1µs may not pass through completely instead only the first transition may get detected while the second transition can go undetected. I see that happening for some of the input pulses.
    Yes, ISO7742 should address this issue. ISO7742 uses OOK architecture as against edge-based architecture of ISO7242A and hence doesn't require a DC refresh signal as it inherently keeps the output match input all the time. ISO7742 also supports much larger datarate and hence, pulses as short as 10ns can still be passed without any issues.

    A2. Could you please share the ADI part number that is tested in place of ISO7242A?
    Like I mentioned in the previous point, ISO7742 architecture doesn't require a refresh signal and it keeps the output matched to input all the time. I would strongly recommend customer to test ISO7742 in place of ISO7242A. Thanks.

    Regards,
    Koteshwar Rao

  • Hi Koteshwar Rao,

    Thank you for your reply.

    1.

    Could you inform me if you have any easy-to-understand documentation of DC refresh and OOK architecture? 

    2.

    >instead only the first transition may get detected while the second transition can go undetected.

    >I see that happening for some of the input pulses.

    →It seems that output(ch2) is inverted compared with input(ch1) on NG2(p4) and NG3(p5) and NG4(p6).

    What do you think is happening with the DC refresh architecture?

     

    3.

    Is there DC refresh frequency dependent?

    For example, if a signal shorter than 1us does not pass through with ISO7242, can the problem be improved by changing to ISO7242M (150Mbps)?

    ISO7742 is recommended, but please tell me the advantage of OOK for DC refresh.

     

    4.   

    ISO7742 architecture doesn't require a refresh signal and it keeps the output matched to input all the time.

    Does this mean that there is no mismatch between the input and output signals (the operation equivalent to the refresh function is always working)?

    For example, is it always updated to match the input/output signals even if the output changes due to the effect of noise?

     

    5.

    The part number is ADuM242E.

    It has OOK architecture. If ISO7742 is advantage about it, could you share it?

     

    Best Regards,

    ttd

  • Hi Koteshwar Rao,

    I add No 6. Could you answer six questions? 

    6. Does the OOK architecture also have a function equivalent to DC refresh? (Function to match input and output signals)

    I understand that DC refresh matches the input and output in the refresh cycle.
    On the other hand, I don't understand how the OOK architecture works.
    (Is the image of the power-up version of DC refresh good?)

    Please tell us if the OOK architecture is effective for this event.

    Best Regards,

    ttd

  • Hi TTD,

    Thank you for sharing additional input and the competition device part number. Please see below my inputs to your questions, thanks.

    1. Yes, please refer to the document from below link titled "Digital isolator design guide" which talks about both edge-based and OOK architectures in brief.

    2. Like I explained earlier, if the input pulse is shorter than 1µs then ISO7242A can may respond to the first transition but may fail to respond to the second transition because the second transition is too soon and the time between first and second transition is <1µs.
    e.g., refer to NG4 waveform. At the start of the waveform, both input and output match (both HIGH). After about 130ms, input goes from HIGH to LOW and then quickly comes back to HIGH. I can't make out the time duration between these two transition, it is possible this is <1µs. Output responds to first HIGH to LOW transition and but cannot respond to LOW to HIGH input transition because this is too soon and possibly in <1µs. Hence output stays LOW while input is HIGH. Ideally the DC refresh should have corrected the output in a few 10s of µs but I see that didn't happen. I would have to understand more about customer application to understand what's going on and why DC refresh didn't work.
    The same applies to NG2 and NG3 as well.

    3. DC refresh rate is fixed and is not dependent on input signal frequency except that DC refresh doesn't come into picture for input pulses shorter than 1µs. Yes, ISO7242M should fix this issue as it has higher input bandwidth.
    Like I mentioned earlier, I would recommend to use ISO7742 because this is our latest digiral isolator family with very good performance overall including high voltage performance.
    As you may have already seen in the digital isolator design guide, OOK uses a high frequency carrier to represent input data. If a carrier is transmitted, it means one input state and if the carrier is not transmitted then it means the other state. This means that the output always knows the input based whether input carrier is present or not and hence a separate DC refresh is not needed.

    4. This is explained in the previous point. Yes, even if the noise tries to change output, the output will always stay forced to match input. This is going to be almost the same as if the input is directly connected to the output.

    5. Yes, ADuM242E is an OOK device similar to ISO7742. I have already explained more about OOK in above points.

    6. OOK architecture and why it doesn't require DC refresh is already explained in above points.

    Let me know if anything is not clear, thanks.

    Regards,
    Koteshwar Rao

  • Hi Koteshwar Rao,


    Thank you for your reply.

    There are "PRODUCT NOTIFICATION" and "Figure 11. ISO724xA Anomaly" about <1μs pulse on datasheet Page.13 of ISO7242A.

    Is it possible to explain the behavior about this case with block diagram  of edge based architecture?


    It seems that this waveform is very similar to my chattering problem.

    Best Regards,

    ttd

  • Hi TTD,

    Thanks for highlighting ISO7242A anomaly. Yes, this is the same anomaly that customer is seeing in their waveform. When a <1µs negative pulse is applied then output gets locked to a LOW state and DC refresh doesn't change the output upto the next rising edge of input outside of the 1µs window from the first negative edge.

    Please note that this is specific to ISO7242A and doesn't apply to any other device including ISO7242C or ISO7242M. Hence, this is not architecture dependent but an anomaly observed only in ISO7242A. If customer uses ISO7742 then they shouldn't see this. Thanks.

    Regards,
    Koteshwar Rao

  • Hi Koteshwar Rao,

    Thank you for your reply.

    I understand only ISO7242A has this problem.

    So my customer has additional two questions. 

    1.) Although ISO7242A has DC refresh (function to match input and output signals),

     Why does the DC refresh function not work and an anomaly occurs when a signal of <1us is input ?

       For example,

          - the function of switching from Low-Frequency Channel to High-Frequency Channel doesn't work correctly when <1us input.

          - The flip flop doesn't latch <1us input correctly.

    2.) Refresh is interpreted as a function to make the input and output signals match each other periodically, regardless of signal changes.

     Please tell us again about the purpose of refreshing.

    Best Regards,

    ttd

  • Hi TTD,

    Please see below my inputs, thanks.

    1. When a negative pulse with duration <1µs is applied, the input filter withholds DC refresh until the next rising edge outside the 1µs window from the first negative edge. For this reason DC refresh doesn't come into action during this time.

    2. You have correctly mentioned the purpose of DC refresh as a function to match input and output signal periodically, provided the device is operated within the recommended operating conditions. Applying <1µs pulse is in violation of recommended operating conditions and hence device operation is not guaranteed under such conditions.
    We did consider broadening device operation even under such violations which may be common in some applications and implemented those considerations for our future devices accordingly though we still do not guarantee complete operation and datasheet performance outside of datasheet recommended operating conditions.
    Thus devices like ISO7242C from the same family do not exhibit this anomaly but we do recommend you to use our latest digital isolator family device ISO7742 which has significant overall improvement compared to older isolator families.

    Regards,
    Koteshwar Rao

  • Hi Koteshwar Rao,

    >1. When a negative pulse with duration <1µs is applied, the input filter withholds DC refresh until the next rising edge >outside the 1µs window from the first negative edge. For this reason DC refresh doesn't come into action during this time.

    →It seems that the input and output are matched at the edge timing (rising edge, falling edge).

     In operation, ISO7242A seems to be waiting for the edge(ISO7242A doesn't know when the edge will come).

     

    >2. You have correctly mentioned the purpose of DC refresh as a function to match input and output signal periodically,

    >provided the device is operated within the recommended operating conditions.

     

    →Regardless of the change in the signal, it seems that the input and output are periodically matched even if the rising and falling edges do not come.

     

    Q3. )

    For DC refresh, is it executed by "change of signal" like 1?

    Or is it executed periodically, "regardless of signal change" like 2?

     

    When DC refresh is executed periodically like 2, I think that even if a signal of <1us is input, ideally it will return to the original normal state at the time when the input and output match is executed periodically (without waiting for the edge).

    Q4. )

    >the input filter withholds DC refresh

    →Does this mean red circle such as following figure?

        Does this situation(withholds DC refresh) mean keeping "AC channel"?

    Best Regards,

    ttd

  • Hi Koteshwar Rao,

    The problem was solved when the customer changed from ISO7242A to ISO7742.
    Thank you for your support.

    For additional ISO7242A questions I posted yesterday,
    I look forward to your answer.

    According to your answer,
    Since DC refresh periodically matches the input and output,
    Even if the output becomes abnormal due to a pulse of less than 1us,
    Ideally, I think that the input and output should match when the DC refresh is executed periodically.
    However, actually, when a pulse of <1us or less is input, the DC refresh is suspended by the input filter.
    Input and output do not match until the next edge arrives.

    There are two contents: DC refresh operates at the edge (Answer 1) and DC refresh operates periodically (Answer 2).
    It would be helpful if you could tell me how to think (Q3, Q4).

    Best Regards,

    ttd

  • Hi TTD,

    Thanks for sharing the information about testing ISO7742 and it working fine.

    Regarding your question on whether DC refresh, DC refresh periodically checks if the output is matches the input and if there is a mismatch, it corrects the output accordingly. This happens periodically even when the input is not changing. The only exception when DC refresh doesn't work is when a negative pulse with <1µs width is applied. Under this condition, the device waits for 1µs irrespective of any changes at the input and after 1µs, device waits for input rising edge. The device starts responding normal only after the first rising edge after the above condition.

    A3: I think the above point about DC refresh answers your question Q3.

    A4: Yes, the block marked with red rectangle is the input filter that makes the device not respond to any input for 1µs and upto the point a rising edge is applied at the input after 1µs time window. No even AC channel will not work until a rising edge after the 1µs window is applied.

    I hope this clarifies all your questions, thank you.

    Regards,
    Koteshwar Rao

  • Hi Koteshwar Rao,

    Thank you for your quick reply.

    >A4: Yes, the block marked with red rectangle is the input filter that makes the device not respond to any input for 1µs and >upto the point a rising edge is applied at the input after 1µs time window. No even AC channel will not work until a rising >edge after the 1µs window is applied.

    →Is it correct to understand that both AC channel and DC channels are not working and consequently DC refresh is not working? 

       DC refresh is executed by AC channel and DC channel.

    Best Regards,

    ttd

  • Hi TTD,

    Both AC and DC channels work separately and the DC refresh is not directly dependent on AC or DC channel. Since DC refresh works in the background, it is not shown in the block diagrams. You can consider that DC refresh is a function that periodically checks output to see if it matches with input and if it doesn't then the DC refresh corrects the output to match the input.

    Regarding the issue related to ISO7242A, lets just understand that ISO7242A has this limitation and this limitation is very specific to one particular test condition and to ISO7242A only, as described below. How exactly this happens inside device would be outside the scope of our discussion as I won't be able to explain it with just a functional block diagram and sharing internal circuit details won't be possible.

    "When a negative-going pulse below the specified 1µs minimum bit width is input to the device, the output locks in a logic-low condition until the next rising edge occurs after a 1µs period. Positive noise edges in pulses of less than the minimum specified 1µs have no effect on the device, and are properly filtered."

    I am happy to know that customer has moved to ISO7742 and since ISO7742 is our latest family of digital isolators, it is expected to offer the best performance.. Thanks.

    Regards,
    Koteshwar Rao