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ISO7710: ISO isolators narrow body working voltage in molded application

Part Number: ISO7710

There is a big differences between a 16-pin SOIC wide-body (DW) and a 8-pin SOIC narrow-body (D). The greatest difference is in the maximum working isolation voltage, DW has 1500 V RMS, while D has only 400 V RMS. There is also a big external clearance difference (DW 8 mm -> D 3.7 mm).

Is it possible to use bigger working voltage in systems when all electronic elements are molded with epoxy resin?

Zajc Franc 

  • Hi Franc,

    Thanks for your interest in ISO7710 and for reaching out to us.
    The difference in external clearance / creepage between the two packages is primarily due to the difference in their physical dimensions. Because of the lower clearance / creepage, the D package cannot be used at higher working voltage.

    When a D package of ISO7710 is molded with epoxy resin, we do expect it to support higher working voltage but our factory testing on D package is done according to the datasheet ratings. Hence, we won't be able to guarantee any higher voltage ratings apart from what is the datasheet.

    May I know what is your working voltage requirement? Any specific reason for not considering to use DW package?

    Koteshwar Rao

  • Thank you for the answer.

    I'm working on Gate driving circuit and power stage consisting of3 parallel SiC power FETs working at 800VDC on one PCB. The complete board with 6 power transistors for 10kW (100Arms) without cooling is very small - only 35 x 89 x 6mm. The switching frequency is up to 500kHz. Due for paralleling and extreme high frequency all distances are also very small. No element on board (except power transistors and capacitors) is bigger than 2 x 3mm.  

    The board has transformers to isolate driving pulses and gate powering.The  ISO7710 is used for transfer power FET short circuit information from high side to low side and from low side to input. There is not possible to make enough creeping distance between elements on the PCB which looks like a cell phone for such a small PCB board without epoxy vacuum molding. The molded board without ISO7710 passed all tests. There is not enough place for bigger ISO housing. Bigger housing will result in additional 3-5 nsec line delay in the circuit. Any additional delay reflects in not synchronous switching of parallel transistors. Power transistors in the application are switching at zero dead time with only 4 nsec interlock delay between switches. 
    My questions are
    -Is there different a chips inside of small and big housing for ISO7710
    _is there different quality of molding material for  small and for big  ISO7710 housing 
    Best Regards
  • Hi Zajc,

    Thank you for sharing the background, this helps me understand the situation better.

    I do see how challenging it is for you to meet your solution size requirement. Please see my inputs below to your questions,

    1. ISO7710 is available in D & DW packages and the design inside of the two is exactly the same.
    2. The molding material is of highest quality already supporting Material Group I.

    The design in D package supports much higher isolation ratings that what is quoted in datasheet and I see that your application is already tested without any issues. Hence, when you use epoxy coating you do expect to meet your requirements better. I do not expect you to see any issues in meeting your requirements when the device is epoxy coated.

    With that said, I do like to point out that our device specifications guarantee will still be limited to what you see in datasheet for D package.

    I see you have used transformers for driving pulses, do you see the possibility of using ISO77xx with epoxy coating for isolating these signals as well? We do expect the digital isolators to offer better performance. Thanks.

    Koteshwar Rao

  • Hi

    Thanks for the information. For me it is very important than inside is the same system and the same molding, so only outside creeping distance is the problem.
    Regarding transformers.
    I use transformers in two points of the driver circuit for simultaneous transfer of 10 to 50nsec high current (10A) pulses to generate over 50A driving current for power FET. Synchronisation between LOW and HIGH side should be less than 2nsec. You can see more on 
    Those short times could not be realised with ISOxxxx coupled with pulse amplification to 50A.
    Thanks again and stay safe