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ISO7721: RS485 Automatic TX enable circuit analysis

Part Number: ISO7721

Hi team,

My customer is using our ISO7721 and SN65HVD3082 to achieve an isolated 485 interface. RS485 need two data signal and two or one control, however they use only one piece ISO7721 to achieve it. They use an automatic TX enable circuit formed by an mosfet switch. Their circuit is just as below. I'm confused by this circuit and could understand how this circuit work. So could you help analysis the circuit working principle? Any comments are highly appreciated.

Thanks and Best Regards,


  • Hi Will,
    Thanks for posting this and we are happy to help!

    Let's break it down into two cases.
    Case 1 : if UARTAO_TXD = VIB = logic 1 ( ~3.3V), then VOB = pin 6 = logic 1 ( = 5V ). This goes into the gate input of N channel FET Q3 (BSS138), which has the source terminal connected to GND_A0 and drain connected to pins 2 and 3 of RS485 chip. So, if input gate signal is high, then the NMOS turns ON and pulls down the drain to ~0V ( = GND_A0). Because of this, DE = 0 and RE_bar (pin2) = 0, which means in RS485 chip, driver is disabled and receiver is enabled. So data from the bus lines A and B can be communicated on to the "R" pin output -> VIA (pin7) input --> UARTA0_RXD output.

    Case2: if UARTAO_TXD = VIB = logic 0 ( ~ 0V), then VOB = pin 6 = logic 0 ( ~0V ). Because of this, the gate input to the NMOS is now low, which means the FET is *off*. This means that the 1K pull-up resistor R95 will passively pull up the drain voltage to 5V. If the drain = DE = RE_bar(pin2) = ~5V, then
    driver is now *enabled* and receiver is disabled. This means that whatever input data is there will get passed onto the RS485 bus. The signal path will now be: UARTA0_TXD->VOB -> D (pin4 of RS485) --> B & A lines on RS485 bus.

    Thus the TXD input controls the data flow .

    I hope this helps!