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ISO3088: Power Sequencing and shut down

Part Number: ISO3088


I will use the ISO3088 in our new design an I want to check first how it's look like with "power sequencing".

In my application VCC1 is 3.3V and VCC2 is 5V. I am making the 5V from 24V with an isolated DC-DC converter.

The 3.3V side is coming from my FPGA and the 5V is outside from our system.

Which supply should be apply first to the IC: VCC1 or VCC2? With which delay?

Can I also just supply the 3.3V (VCC1) without supplying the 5V side (VCC2) without any damage?

I am thinking to do this when I don't use the chip, or will you recommend to use it as an Input  when not use (DE low and /RE low)?

for example in this way I can use an internal register in my FPGA to ignore the input and connect DE and /RE together.

Many thanks for your feedback.

Best Regards,


  • Hi Xavier,

    ISO3088 do not require any specific power sequencing (unless required by your application). You may power up VCC1 and VCC2 in any order, but just keep in mind that the bus (A/B and Y/Z) and D/R pin states will follow below state as mentioned in datasheet.

    Hope this answers your question. Please let me know if you have further queries.



  • In reply to Tejas Hommaradi:

    Dear Tejas,

    many thanks for your help.

    I check the different state and it matching what I need.

    So it should be work as we want to use it.

    Best Regards,