• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 16 subscribers
  • Views 1103 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISO1541: Secondary Side Clock Gapped

John W Wallace
Prodigy 190 points
Part Number: ISO1541
Other Parts Discussed in Thread: ISO1540

Having Issues with the Slave side clock disappearing at the output side (Side 2) of our ISO1541.  Master is a Xilinx FPGA connected to Side 1 of the ISO1541, Slave is a Delta Power Supply.  We are trying to perform PMBus operations and are unfamiliar with PMBus though it seems I2C/SMBus are the PHY layer of the comm link.

It seems that the Clock disappears from the output of the ISO1541 after the slave ACKs a transaction. Below is a scopeshot of the Controller side SDA, SCL and the Slave side SCL.  

Could this be the slave stretching the clock?  I've never come across clock stretching so am unfamiliar with it.

Thanks for the help

-Jack

  • 0
    TI__Intellectual 2900 points
    Hi Jack,

    As you said, this looks like the slave is pulling down the clock. This doesn't seem to be an issue with the ISO1541.
    Could you please share a rough schematic of the section related to ISO1541, to help us better understand the system?
    Also it looks like your clock speed is approximately 100kHz. Have you checked the specification of the Delta power supply whether it is capable of handling the required speeds?

    Regards,
    Anand Reghunathan
  • 0 in reply to Anand Reghunathan
    Prodigy 190 points

    Hi Anand,

    Thanks for the quick reply.  To confirm your suspicions, we are operating the bus at 100K and have confirmed this bus speed with the PSU datasheet.  The PSU Mfr, has also confirmed that the unit will throttle the clock "if there is a mismatch between the system clock and the psu".  Not sure what is meant by "a mismatch" between clocks.  However, PMBus is somewhat strange, in that the I2C format is not

    [Start][Device Address][R/Wn][ACK][Register Offset][Stop]  [Start][Device Address][ACK][Data1][Data2]...[DataN][Stop]

    Instead, [Register Offset] is replaced by [Command].  Where in a PSU I imagine a [Command] could be, Read an ADC to get a Thermistor Measurement or some other such thing that may take longer than just spitting out the contents of a memory location.  Thus, the need for clock stretching on the slave's end.

    We are going to try and switch out the ISO1541 with the ISO1540 which has the Bidirectional Clock to see if this will remedy our problem.

    I've uploaded a snippet of the schematic pertinent to this issue in both a .jpg and .png formats.  For some reason it doesn't preview.