Part Number: ISOW7842
Hi I am using ISOW7842 in my design and due to which my product is failing radiated emission test. There is very high emission at around 66MHz.
Can someone help me out to reduce the radiation level to pass the product.
That's a familiar story.
I'm using ISOW7841 and am failing CISPR11 Level B at 65MHz, despite taking several steps recommended in the application note for the ISOW784x parts.
I was failing even level A but adding common mode chokes to the input and output supplies to the isolator and ferrite beads to supply and ground connections as shown in the note has reduced the radiated noise considerably.
The only way I've found to reduce the noise below level B is a conductive screen above (and maybe below) the ISOW7841. The screen doesn't have to be grounded or extend very far from the isolator to be effective. Unfortunately, incorporating this into production units will be tricky and the product is double insulated in a plastic enclosure.
The sniffer probe suggests there is a stray field above the part. A horizontal loop produces a peak above the chip, a vertical loop produces a null above the chip with peaks either side. I am assuming this is from the power transfer device (transformer?). I am also going to try making some kind of magnet circuit around the chip with ferrite sheets to see if that works but a conductive screen looks favourite for now.
If anybody has any other ideas, please chip in....
In reply to Alex Ballantyne:
In reply to Koteshwar Rao:
Thanks for your suggestions, I'll try those ferrites as soon as I can.
I'm curious about the effectiveness of screening though. If I cover just the top of the ISOW with aluminium foil, emissions are significantly reduced.
Can you suggest a mechanism for this? I want to avoid having a screen if at all possible so better filtering is attractive if it works....
Unfortunately, ISOW7841 alone does not a product make....
I tried with ferrite bead also but did not see any improvement in emission level. Even i tried with different combinations of decoupling capacitors.
Can you suggest some other way to reduce the emission level.
I have revisited Section 7 and note that the test board for ISOW7841/7842 is sitting on top of the box lined with a screen.
I think that provides an partial screen for the chip and will be reducing emissions compared to what would be seen with the board placed on the table.
Our product has no conductive enclosure so the test set-up cannot be reproduced in our tests, without adding an screen somehow.
In reply to Dileep Motwani:
Thank you for your interest in this.
I have to admit, I didn't think stitching capacitance would be a factor at 65MHz. In SLLA386, Figure 10, there seems to be no difference between the emissions at 60MHz between the two cases, with and without stitching capacitance.
In our design, there is a 220pF THT capacitor between the ground planes. This part has an SRF >100MHz so I expect it to still be quite effective at 65MHz. Figure 10 only shows the effect of the stitching capacitance above 200MHz.
I understand that there is no foil on top of the box in Figure 14 but the lining of the box must be just one or two mm from the DUT and will still be a pretty effective screen for one side of the DUT.
In reply to Dan Kisling:
Thanks for following up.
I have a modified board going into pre-compliance testing on Monday.
I have added ferrite beads to all the signal lines to the ISOW, in addition to those already present on all the cable connections off the board and on the ISOW power supply.
I also have a case with screening to try out if that doesn't work out.
I'll report back when I get the results....
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