I am looking for a solution to isolate a clock signal used by an ADC. As the sampling clock jitter affect a final ADC performance (SNR) I am looking for as minimum jitter introduced by the isolation barrier as possible. Are the digital isolators suitable for such application? Looking at the fastest TI devices, e.g. ISO721M they introduce jitter as much as 1ns (pk-pk) typical. Are there better performing parts in the TI portfolio? The jitter specification is shown in the documentation for a random data pattern and an NRZ pattern, the second is lower so am I right that for a clock signal it will be further improved?
Thanks,
Robert