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ISO7740: Is UVLO implemented to the primary side (VCCI side) or the secondary side (VCCO side) or both?

Part Number: ISO7740
Other Parts Discussed in Thread: ISO7741

 Hello guys,

 One of my customers is evaluating ISO7740 (no F version). Then they observed a short H level pulse on OUTx with L level INx.when VCCI and VCCO was powered up.

 At this moment, VCCI supply voltage was powered up 2~3ms earlier than VCCO powered up. The short H level was observed when the secondary power supply voltage exceeded about 2V.

 Given this, I have a few questions as the follows.

 Q1. Is UVLO implemented to the primary side (VCCI side) or the secondary side (VCCO side) or both?

 Q2. Is OUTx kept H level (default value) until UVLO is released (until the secondary power supply voltage exceeded about 2V)?

 Q3. If Q2 is true, which page of the device datasheet is it described? (I couldn't find the description about the default condition in the datasheet 

 Could you please give me your reply? Your reply would be much appreciated.

 Best regards,

 Kazuya.

 

  • Hi Kazuya,

    Thank you for posting to E2E! In short, yes, UVLO is implemented on both sides of the ISO7741 isolator. There is a brief period of time (on the order of micro-seconds) during power up where an output will follow the device's default output state before following the channel input. This is not specified in the device datasheet, but if a low state is required please do use an ISO7741F unit as mentioned in the previous post below:




    Thank you,
    Manuel Chavez

  •  Hi Manuel,

     Thank you for the prompt reply.

     I will recommend the customer to use F version strongly.

     Thank you again and best regards,

     Kazuya.