Other Parts Discussed in Thread: ISO7741
Hello guys,
One of my customers is evaluating ISO7740 (no F version). Then they observed a short H level pulse on OUTx with L level INx.when VCCI and VCCO was powered up.
At this moment, VCCI supply voltage was powered up 2~3ms earlier than VCCO powered up. The short H level was observed when the secondary power supply voltage exceeded about 2V.
Given this, I have a few questions as the follows.
Q1. Is UVLO implemented to the primary side (VCCI side) or the secondary side (VCCO side) or both?
Q2. Is OUTx kept H level (default value) until UVLO is released (until the secondary power supply voltage exceeded about 2V)?
Q3. If Q2 is true, which page of the device datasheet is it described? (I couldn't find the description about the default condition in the datasheet
Could you please give me your reply? Your reply would be much appreciated.
Best regards,
Kazuya.