Part Number: ISO1540
Customer design ISO1540 for I2C interface and below is their application diagram, they want to know is this kind of design ok or not?
They concern signal voltage level and quality, please advise.
BTW, they also plan to use TCA9617A or TCA9800 in connected with ISO1540.
Thank you for reaching out to us for the review. The approach followed by customer is okay, I just a few questions and comments to understand the requirement better. Thanks.
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In reply to Koteshwar Rao:
From this table, it seem our output1 low level will between 0.65V to 0.8V.
So I think if your device input low level max value is 0.8V then there is no margin.
But I think due to our max value is 0.8V (ISDA: 0.5mA~3.5mA), so there can’t have any voltage tolerance in this condition.
Based on my knowledge, maybe you still need to consider higher input low level device, ex: 0.9V
customer confirm it is only this connection based on their system
yes, only one salve
In reply to Paul Yeh:
Thank you for your inputs. Please see my comments below.
TCA9617A based solution:I see that slave VOL is 0.4V max while TCA9617A SideB VIL is 0.4V max. Seems there is no margin in this case, hopefully this still is okay. Similarly, VOL of ISO1540 Side2 is 0.4V max while VIL of Master is 0.4V max. No margin here either.
TCA9800 based solution:
TCA9800 SideB is compatible to slave but ISO1540 Side2 VOL has no margin to VIL of Master just like in previous solution. I recommend the following changes which makes all devices compatible to each other. Thanks.
Master <---> <SideB-TCA9800-SideA> <---> <Side1-ISO1540-Side2> <---> Slave
=> Since TCA9800 Side B cannot be connected with Static-voltage offset Side. Master side PCA9617A for SDAB, SCLB, Is there any problem with this? And is there any way to reduce ISO1540 Side2 VOL.
Thanks for additional inputs. PCA9617A is also buffer/repeater and hence, it is not the master here. Hence, could you please confirm what device is connected to PCA9617A SideA?
Like I mentioned earlier, ISO1540 Side2 VOL is 0.4V max while PCA9617A VIL is 0.4V max as well. This should work for most cases but I am only highlighting that there is no margin in the VIL and VOL specs. Thanks.
They need to check another engineer who design master board for connection. and below is their configuration. FYI
my customer is designed power board.
one more question is , VOLMAX=0.4V and VIL=0.8V is max value. but if they design buffer/repeater's static-voltage offset side, there would be no margin problem? is it general situation?
Corrected one picture.
Thank you for sharing additional information including master I/O thresholds.
I see that master I/O specifications are good and don't have any concerns there. But my previous comment of there being no margin between TCA9617A & slave and between ISO1540 and PCA9617A. They all are compatible but no margins. I am re-sharing my earlier comments on the concern I had mentioned earlier.
TCA9617A based solution:I see that slave VOL is 0.4V max while TCA9617A SideB VIL is 0.4V max. Seems like there is no margin in this case, hopefully this still is okay. Similarly, VOL of ISO1540 Side2 is 0.4V max while VIL of PCA9617A is 0.4V max. No margin here either.
In addition, I also see that ISO1540 Side2 may also need to connect to IPMI device. I am not sure about IPMI I/O thresholds but that also need to be compatible with ISO1540 Side2. Thanks.
Please see my inputs below, thanks.
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