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ISO1540: Customer would like to double check application design

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Replies: 10

Views: 199

Part Number: ISO1540

Hi team,

Customer design ISO1540 for I2C interface and below is their application diagram, they want to know is this kind of design ok or not?

They concern signal voltage level and quality, please advise.

BTW, they also plan to use TCA9617A or TCA9800 in connected with ISO1540.

Thanks

Regards,

Paul

Texas Instruments

 

  • Hi Paul,

    Thank you for reaching out to us for the review.
    The approach followed by customer is okay, I just a few questions and comments to understand the requirement better. Thanks.

    1. Do you know why does customer intend to use the I2C buffer between ISO1540 and slave? Is there any particular reason?
    2. Side1 of ISO1540 is usually meant to be connected to a single master or slave while Side2 supports multiple I2C nodes connection as it supports higher bus capacitance and load current. So If Side1 I/O logic thresholds of ISO1540 are compatible with the master then I recommend connecting Side1 to master.
    3. Can you confirm if there is only one master and one slave this application or if there would multiple slaves connected to the I2C bus?
    4. Could you please share the VIL, VIH and VOL thresholds of master and slave just to make sure they are compatible with ISO1540. Alternatively, you could give me the part numbers of master and slave devices.

    Regards,
    Koteshwar Rao

  • In reply to Koteshwar Rao:

    Koteshwar,

    1.

    From this table, it seem our output1 low level will between 0.65V to 0.8V.

    So I think if your device input low level max value is 0.8V then there is no margin.

    But I think due to our max value is 0.8V (ISDA: 0.5mA~3.5mA), so there can’t have any voltage tolerance in this condition.

    Based on my knowledge, maybe you still need to consider higher input low level device, ex: 0.9V

    2.

    customer confirm it is only this connection based on their system

    3.

    yes, only one salve

    4.


     

    Regards,

    Paul

    Texas Instruments

     

  • In reply to Paul Yeh:

    Hi Paul,

    Thank you for your inputs. Please see my comments below.

    TCA9617A based solution:

    I see that slave VOL is 0.4V max while TCA9617A SideB VIL is 0.4V max. Seems there is no margin in this case, hopefully this still is okay. Similarly, VOL of ISO1540 Side2 is 0.4V max while VIL of Master is 0.4V max. No margin here either.

    TCA9800 based solution:

    TCA9800 SideB is compatible to slave but ISO1540 Side2 VOL has no margin to VIL of Master just like in previous solution. I recommend the following changes which makes all devices compatible to each other. Thanks.

    Master <---> <SideB-TCA9800-SideA> <---> <Side1-ISO1540-Side2> <---> Slave

    Regards,
    Koteshwar Rao

  • In reply to Koteshwar Rao:

    Koteshwar,

    Following question.

    => Since TCA9800 Side B cannot be connected with Static-voltage offset Side. Master side PCA9617A for SDAB, SCLB, Is there any problem with this? And is there any way to reduce ISO1540 Side2 VOL.


    Regards,

    Paul

    Texas Instruments

     

  • In reply to Paul Yeh:

    Hi Paul,

    Thanks for additional inputs. PCA9617A is also buffer/repeater and hence, it is not the master here. Hence, could you please confirm what device is connected to PCA9617A SideA?

    Like I mentioned earlier, ISO1540 Side2 VOL is 0.4V max while PCA9617A VIL is 0.4V max as well. This should work for most cases but I am only highlighting that there is no margin in the VIL and VOL specs. Thanks.

    Regards,
    Koteshwar Rao

  • In reply to Koteshwar Rao:

    Koteshwar,

    They need to check another engineer who design master board for connection. and below is their configuration. FYI

    my customer is designed power board.

    one more question is , VOLMAX=0.4V and VIL=0.8V is max value. but if they design buffer/repeater's static-voltage offset side, there would be no margin problem? is it general situation?

    Thanks

    Regards,

    Paul

    Texas Instruments

     

  • In reply to Paul Yeh:

    Koteshwar,

    Corrected one picture.

    They need to check another engineer who design master board for connection. and below is their configuration. FYI

    my customer is designed power board.

    one more question is , VOLMAX=0.4V and VIL=0.8V is max value. but if they design buffer/repeater's static-voltage offset side, there would be no margin problem? is it general situation?

    Thanks

    Regards,

    Paul

    Texas Instruments

    Regards,

    Paul

    Texas Instruments

     

  • In reply to Paul Yeh:

    Hi Paul,

    Thank you for sharing additional information including master I/O thresholds.

    I see that master I/O specifications are good and don't have any concerns there. But my previous comment of there being no margin between TCA9617A & slave and between ISO1540 and PCA9617A. They all are compatible but no margins. I am re-sharing my earlier comments on the concern I had mentioned earlier.

    TCA9617A based solution:

    I see that slave VOL is 0.4V max while TCA9617A SideB VIL is 0.4V max. Seems like there is no margin in this case, hopefully this still is okay. Similarly, VOL of ISO1540 Side2 is 0.4V max while VIL of PCA9617A is 0.4V max. No margin here either.

    In addition, I also see that ISO1540 Side2 may also need to connect to IPMI device. I am not sure about IPMI I/O thresholds but that also need to be compatible with ISO1540 Side2. Thanks.

    Regards,
    Koteshwar Rao

  • In reply to Koteshwar Rao:

    Koteshwar,

    Two questions:

    1. Customer knew it is compatible w/o margin now. but they would like to know is there any risky here?
    2. And Based on SMBUS's standard, VOL=0.4V max and VIL=0.8V max,  but if only connecting Static-voltage offset Side will have no margin, so is there any approach to increase margin?

    Thanks

    Regards,

    Paul

    Texas Instruments

     

  • In reply to Paul Yeh:

    Hi Paul,

    Please see my inputs below, thanks.

    1. Ideally there should not be any risk in using it without any margin.These are worst-case values and very rarely the device will hit these levels.
      1. The only concern is when the devices are placed far from each other and the PCB layout is not optimum. In such a case, there could be some voltage drop in the path leading to the levels exceed. Again this is also very rare.
    2. Since both master and slave have not so convenient specs, it is difficult to improve this. The solution that is achieved currently is the best that can be done.

    Regards,
    Koteshwar Rao