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# ISO7742-Q1: VDDX UVLO+/- THRESHOLD

Part Number: ISO7742-Q1

Hi team ,

I am using ISO7742F in my project application. During validation, I find that the VDDX UVLO threshold values as mentioned in the datasheet is not matching with my results.

I have provided 3.3V to VCC2 and IND on Side B and VCC1 = 5V/400ms on Side A.

According to the datasheet, VCC(UVLO+) should be in the range of 2V to 2.25V and VCC(UVLO-) should be 1.7V - 1.8V

But I am observing  VCC(UVLO+) = 1.959V and VCC(UVLO-) = 2.025V.

Could you please explain the deviation?

• Hi Anne,

Welcome to TI E2E Forum!

Thank you for reaching out to us and sharing details related your question.

Please note that the VCC(UVLO+) is 2V typical and 2.25V max which means that on a typical sample you should see a voltage of 2V while it can always be lower based on the sample you are testing but should never be higher than 2.25V.
Similarly, 1.8V is a typical VCC(UVLO-) value while the value can always be higher based on the sample but will never be lower than 1.7V.

The particular sample you are testing does seem to have slightly off typical values but this shouldn't be the case with all the samples. If all the samples you have share the same lot trace code (top marking) then it is possible to see similar results across all those samples. I would recommend ordering a fresh batch of samples and testing them under the same conditions.

Let me know if you have any other questions, thanks.

Regards,
Koteshwar Rao

• In reply to Koteshwar Rao:

Hi Koteshwar,

Thanks for your response.

Could you also explain why the output seems to be gradually increasing like this, instead of appearing like a pulse?

• In reply to Anne Vilasini:

• In reply to Anne Vilasini:

Hi Anne,

The typical HIGH output voltage (VOH) for output pins is going to be "VCC-0.2V", for your case OUT = VDD1-0.2V. Since VDD1 is either increasing or decreasing in your tests, the voltage at OUT pin is also expected to follow VDD1. Hence, this is expected.

1. Could you please confirm if there was any load or capacitor connected at output pin that is being monitoring?
2. The output waveform is quite zoomed out and there could be measurement error involved.
1. Hence, please monitor only UVLO+ or UVLO-, one at a time.
2. Please keep the oscilloscope triggered to the output pin maybe at 1V and run the test.
3. Please also keep the time division in scope to 100ns/div. It is currently set to 400ms/div. This avoids the error in measurement and VCC voltage will look pretty flat in scope at this time scale.
4. Repeat the test for UVLO+ and UVLO- separately.

Once you do the above test, please do share us the waveform. Thanks.

Regards,
Koteshwar Rao

• In reply to Koteshwar Rao:

Hi Koteshwar,

There is no load or any capacitor connected to the output pin.

Further, I have performed the test as suggested. I have attached the waveforms below. As you said, I could now clearly monitor UVLO+ and UVLO- thresholds. Please have a look at the waveforms and let me know your thoughts.

UVLO+

UVLO - :

• In reply to Anne Vilasini:

Hi Anne,

Thanks for testing according to the suggestion and sharing the waveform quickly.

The UVLO+ waveform seems pretty clear and hence 1.8V seems to be the accurate UVLO+ value. For UVLO-, I see that the output voltage doesn't fall down to 0V quickly. This is because after the device goes into UVLO the output becomes Hi-Z and hence, there is no discharge path for the voltage across output cap.

Only for the testing purpose, could you please connect any load resistor with 100Ω to 1kΩ at OUT pin to its respective GND? This makes the output voltage fall down quickly and the VDD1 voltage that you read will be the accurate UVLO- voltage. Thanks.

Regards,
Koteshwar Rao

• In reply to Koteshwar Rao:

Hi Anne,

Did you happen to consider the suggestions I have made in my previous post and redo the measurements for UVLO-?

Regards,
Koteshwar Rao

• In reply to Koteshwar Rao:

Hi Koteshwar,

I have not performed the test yet , but there was already a 100 ohm resistor connected to the output pin when I performed the experiment. I gave the wrong information earlier regarding the presence of load.

Also according to this graph in the datasheet provided below,  UVLO + threshold at ambient temperature is somewhere around 2V and it is not less than 2V even at -55 deg C.

According to the test result, our value for UVLO+ is 1.8V. Do you think it is acceptable?

• In reply to Anne Vilasini:

Hi Anne,

Thanks for the update and for confirming that there is 100Ω load already used at the output data channels. If a load of 100Ω is used at the VOUT3, then the output should have fallen down to 0V in <5ns of time upon UVLO- but I do not see that happening in the UVLO- waveform that you have shared. The fall time is not really device dependent but dependent on the load connected. I am worried that maybe there is some issue in load connection to device.

Regarding your question on the graph, 2V of UVLO+ is the expected value for a typical sample while lower values are possible they are considered to occur very rarely. To further identify if there is any issue in device, test approach or test setup, will you please be able to test for UVLO+ and UVLO- on at least 3 samples according to my test recommendations for UVLO+ and UVLO- separately?
This should help us to identify if there is any issue in device, test approach or test setup. Thanks.

Regards,
Koteshwar Rao

• In reply to Koteshwar Rao:

Hi Anne,

I hope you are considering to test more samples for UVLO+ and UVLO- according to the procedure I have outlined above. Once you get the data, please do share with us.

Meanwhile, I will mark this E2E thread as closed. Once you test other samples and if you see any discrepancies, please do not hesitate to reply back to this E2E thread. Thanks.

Regards,
Koteshwar Rao