Part Number: ISO1042
When I am connecting a certain Number of CAN Nodes to the Network, the CAN bus does not work properly anymore. The reason is, as far as i know, that the output levels of the transceivers (Only ACK) are too high. With one device the bus still looks good. With each additional participant the ACK level becomes higher and higher. This is a Problem, because of the static parasitic capacitance of the System the ACK Signal on the RX side is about 260ns longer than it should be. In Response, the CAN interface returns a bus error and the system does not work reliable.
How can I fix this issue?
Thanks a lot!
ACK Level too high, thus ther's a delayed RX Signal
Welcome and thanks for using e2e!
I appreciate the wavefroms. Yeah looking at them I can see the parasitic capacitance at work. I have a few requests for some more info that will help with the debug.
1. How many devices are you adding to the bus? How many until the transmission gets unreliable?
2. Can you provide a schematic of the CAN transceiver and the relevant components for it? I would like to see how you are terminating the bus.
3. What kind of wiring harness are you using for the bus? Is it the proper twisted pair?
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
Hi, and welcome to E2E!
This is an excellent demonstration of what can happen with a large CAN network. During the arbitration and ACK phases, multiple CAN nodes may be driving the bus simultaneously. Often during the ACK bit, many if not all receiving nodes will drive the bus at the same time, resulting in a very strong equivalent drive strength. Driving such a large differential may become an issue if the RC characteristics disallow the dominant-to-recessive edge from transitioning in an acceptable time period.
To solve this issue, there are a few approaches you may consider. The first is to address the RC characteristics of the bus to decrease the dominant-to-recessive transition time. This can be done by either reducing bus capacitance (sources include long cables, excess nodes, or included denoising capacitors) or by decreasing the resistive value between CANH and CANL (slightly smaller termination resistors may be used to do this. Take care that the load does not become too great for any one node to individually drive a valid differential). A second, less targeted approach would be simply to reduce the number of active nodes on the bus. This is likely the more difficult solution to implement because it would include identifying uninvolved nodes and removing them (permanently or temporarily in real time) from the bus. If the first option is not desirable in your design, let me know if you'd like more information on how to accomplish this second option.
My initial suggestion would be to eliminate stray bus capacitance where possible and then considering reducing the value of the termination resistors. If this does not work, please share the tested termination values and placement as well as any bus capacitance measurements you have taken.
Let me know if you have any other questions.
In reply to Lucas Schulte9:
thank you for your response.
1. I am getting Bus-Errors if I am adding more than 45 devices. But I am able to measure the higher Level as soon as I am adding more than five.
3. There is no cabled Bus. This is a System containing PCB's wich are connectet via a Backplane.
In reply to StefanG:
Looks like the termination is good. You are only terminating the ends of the CAN network right? Not every node should be terminated.
It looks like the enemy here in the capacitance on the bus. The PCB back plane is most likely contributing to this to some degree. Also, the TVS diodes also add an amount of capacitance. I don't see a part number on the schematic so I can't see if it is unreasonably high. I would check to see if it is though.
thank you for your Response.
The TVS Diodes have a specified capacitance of around 60fF at 250MHz. So this should be no Issue. It adds a differential capacitance of around 4,2pF in the worst case.
I will make some testing today and you'lll get some Feedback.
Let me know how the testing works out.
You could also lower termination resistance down to a point that would overcome the stray capacitance on the bus. The trade off is heavier bus loading and you most likely wouldn't be able to have a large amount of nodes on the network.
I haven't heard from you in a while. Hopefully you've been able to resolve the issue. I'm marking this as resolved for now but feel free to create a new thread if you have more questions.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.