Part Number: ISOW7840
We're using the ISOW7840DWER to isolate a digital signal prior to it reaching the transmitter. While it appears that we've set up the chip correctly we see that one or two bits of the 32 bit message drop low regardless of the decoupling capacitance. The design originally utilized 0.1uF caps on the VDD and V_ISO pins, however, we saw between 6 and 10 bits drop below the logic threshold. These cap values were increased to 94uF on the VDD line and 47uF on the V_ISO line and the failed bit value was decreased to 1 or 2 per message, but we still see a sudden voltage drop on the failed bits
Sorry to hear about the issue and thanks for reaching out.
Sorry, I am not familiar with ARINC 429 interface but I do see that this is an avionics data bus standard. Could you please help me understand what are the electrical specifications for this interface? I see CH3 and CH4 seem to have bipolar outputs where the signal swings between positive and negative voltages. ISOW7840 data channels do not support bipolar input / outputs.
I see that you have mentioned CH1 (yellow) as the output of ISOW7840 and also referred to pre-isolator signal. Which one is the pre-isolator signal?
Please do also note that ISOW7840 is a digital isolator that integrates a DC/DC converter as well. The DC/DC converter needs a bulk cap for it to operate normal and hence a minimum of 10µF capacitance at both VCC and VISO are necessary while to support transient current requirement by data channels, an additional 0.1µF capacitor should also be used. The order of placement of these capacitors is also important, please refer to ISOW7840 datasheet for layout example in Section 12.2.
Please do share the above requested information along with the schematic so that I can review and comment on the issue. Thanks.
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In reply to Koteshwar Rao:
While we haven't specifically set up the isolator with the 10 uF and 0.1 uF in parallel we did have each value by itself. Obviously this would change some characteristics, but I don't believe it alone would cause the number of dropped bits that we saw coming out of the isolator prior to increasing that capacitance.
As for your other points, the CH 3 and CH 4 lines are far beyond the isolator and are only present on the plot to get an idea of the output from the system on the specific communication bus. The actual signals passing through the isolator are digital waveforms between 0 and 5 VDC at a frequency well below what the isolator should be able to handle.
Additionally, I'm unable to share the schematic on this open forum, but can send something via a message if desired.
Thank you for your help.
In reply to Logan Foley:
Thanks for your inputs. I have reached out to you over email as per your request, thanks.
Thanks for sharing additional information over email. Please do consider incorporating the suggestions provided and let us know your feedback once you test. Thanks.
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