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Schematic Review of TPS3803-01-Q1

Hello,

I would like to have my schematic reviewed, which uses the TPS3803-01-Q1. I am trying to avoid having the PDB pin which is pulled-up to 2.8V come up before the 1.8V rail has come up. It should be GND until 1.8V rail is stable.

My goal is to provide 2.8V to a reset pin on a separate device. However, this reset pin requires this valid high level to be 2.8V, and only after the 1.8V rail has come up. This rail comes up after 2.8V. The power sequence of the system is currently 3.3V -> 2.8V -> 1.8V. VDD is connected to 3.3V, 1.8V is connected to sense through the external resistor divider, and 2.8V is on the /RESET pin. I connect VDD to 3.3V so the open-drain output is controlled and set to drain before 2.8V comes up. Otherwise, the reset pin of the separate device tracks the 2.8V ramp which is undesirable.

On the SENSE pin, I have a resistor divider of 10k for the top resistor and 22.1k for the bottom resistor to give a VIT of 1.78V.

Finally, could a small capacitor of roughly 100nF be added to the output to increase the delay of the output?

I've attached my schematic here. The TPS3803-01-Q1 is at the bottom of page 2.

Please let me know if anything is unclear.

1220.TIDA-01003 Preliminary Schematic.pdf