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TPA3110D2-Q1: the voltage of GVDD when SDB = Low

Other Parts Discussed in Thread: TPA3110D2-Q1

Dear all,

In our experiment, the voltage of GVDD changed when SDB be Hi to Low.

When SDB was Hi, GVDD was 6.91V.

When SDB was Low, GVDD was 5.1V.

We think that GVDD will not change the voltage by SDB from data sheet.

Will internal LDO regulator change something when SDB be Hi to Low?

Could you teach us the voltage of GVDD over temperature when SDB = Low?

Best regards,

  • Hi Yamamoto-san,

    I've assigned this post to the appropriate applications engineer, she will respond to your question.

    Regards,
    Karl
  • This is normal behavior. GVDD is not needed when the device is in shutdown, so the architecture of the part causes the voltage to drop a little. I will check if there is any data about how the GVDD voltage changes over temperature. Why do you need to know how much it varies while the device is in shutdown?

    Thanks,

    -Clancy
  • Dear Clancy,

    Thank you for your reply.

    We need this data because we must calculate the total power consumption of circuit.

    The power consumption is key point for application.

    So we need this data within a few days.

    Thank you very much for your help.

    Best regards,

  • Yamamoto-san,

    I double checked all of the characterization data we have for this device and could not find anything for the GVDD voltage in standby mode. For your worst case power consumption calculations, you could use the normal voltage of GVDD. A lower voltage will actually reduce the power consumption.

    The next best thing I could do would be to test one unit across temperature. If that will be helpful, please let me know and I will complete the test.

    -Clancy
  • Dear Clancy,

    Thank you very much for your check.

    And I could understand the way to calculate the worst power consumption.

    However, I need to know the power consumption in standby mode.

    Could you test one?

    I would appreciate for your help.

    Best regards,

  • Dear Clancy,

    Thank you for your always help.

    How is progress about the test of GVDD voltage?
    I would appreciate if you teach me by when will you answer.

    Best regards,
  • Thank you for your patience. I will be able to take the GVDD voltage measurement across temperature early next week.
  • Dear Clancy,

    Thank you for your support.
    How is progress?
    I am looking forward hearing from you.

    Best regards,
  • Dear Clancy,

    Any update on this issue?
    Your immediate response is highly appreciated.

    Best regards,
  • Yes, here is the data:

    All of this was done with the device in shutdown.

    • PVCC = 8V
    • T=-40C, GVDD = 4.123V
    • T=25C, GVDD = 4.141V
    • T=125C, GVDD = 4.149V
    • PVCC = 10V
    • T=-40C, GVDD = 4.902V
    • T = 25C, GVDD = 5.038V
    • T = 125C, GVDD = 5.136V
    • PVCC = 18V
    • T=-40C, GVDD = 4.939V
    • T = 25C, GVDD = 5.098V
    • T=125C, GVDD = 5.333V
    • PVCC = 25V
    • T = -40C, GVDD = 4.952V
    • T=25C, GVDD = 5.104V
    • T = 125C, GVDD = 5.350V

  • Dear Clancy,

    Thank you very much for your support.

    By the way, why does GVDD decrease to 4.1V in shutdown?
    This IC has LDO, and I think that LDO will not change its output voltage without input voltage changing.

    Could you answer the mechanism why this output voltage changing happen?

    *I know you are busy, but could you answer ASAP? within this week?
    In previous question, my customer has waited for long time...

    Best regards,
  • Yamamoto-san,

    The GVDD voltage is the high-side FET gate drive supply, which is not needed while the device is in shutdown mode. Most likely the feedback is changed so that the LDO output lowers, which improves the power consumption while in shutdown mode.

    Thanks,

    -Clancy
  • Dear Clancy,

    Thank you for your answer! It is very helpful.

    What is the mean of 'feedback is changed'?

    Does feedback resistor is changed? or reference voltage is changed?

    Why does GVDD decrease to only 1~2V at shutdown?

    If GVDD is not needed, is it good to stop GVDD (= 0V)?

    Is decreasing GVDD expected action for designer?

    It is sorry for detail question.

    Best regards,

  • Yamamoto-san,

    I have not seen the internal design for this feature, so I am speculating as to how the LDO voltage is changed.  If the reference is changed, then changing a resistor somewhere would probably be the easiest method.

    When designing with the TPA3110D2-Q1, you should not force GVDD to ground.  The TPA3110D2-Q1 will handle the GVDD output.  As soon as the device exits shutdown mode and returns to normal operation the GVDD voltage will regulate normally.

    Is the customer planning on using the GVDD voltage for something else in their system?

    Thanks,

    -Clancy