Load influence of TWL1200-Q1

Nagasawa san,

We have assigned this thread to the proper application engineer. Please be patient for the answer.

Best regards,
Jason Liu

Nagasawa-san,
please let me know if you are driving it using a push-pull or open drain driver?
Why did you use series termination (22Ohm on each driver output)? According to the application circuit example (datasheet page 23) as well as Design guidelines found in www.ti.com/.../getliterature.tsp;keyMatch=twl1200&tisearch=Search-EN-Everything no external termination is used. The double pulse on Waveform 1 looks like a reflection. Please replace the 22Ohm with a 0Ohm. Please also maintain a controlled impedance of the entire signal path (including connectors as far as as possible).
Best regards,
Frank Dehmelt

Hello Frank-san

I appreciate your quick response.

22 Ohm resistance was placed  for the  noise  and  overshoot.

They try to replace 22Ω　to 0Ω　and there is overshoot and ringing in waveform.(We are getting waveform and send you soon)

SOC driver output is open drain in the period of  initialization.

And after communication beginning ,It becomes the push-pull.

Regards

Tomohiro Nagasawa

Nagasawa-san,
could you please share the scope-plot with the 22Ohm series-resistors replaced by 0-Ohm?
In the XLS-file you had shown the unstable input signal: I understand that this is driven by the SoC? Please check the drive capability of the SoC on its output.
You refer to FPC and TFT board, please clarify which connections are those (Input to TWL1200 or output of TWL1200)?
Furthermore, I think I misread the statement "it is short between SD connector and FPC": You actually refer to a short line-length between SD and FPC? Please check the parasitic capacitance of the "long" connection (Is this board-trace or cable?). Note, both cable and PCB-trace could have several pF/centimeter, so a decent length will add capacitive loading and may even exceed the 75pF Also consider output capacitance of the TWL1200 and input capacitance at the load! Can you run a simulation of the PCB-trace and/or cable to determine the capacitive loading?
Best regards,
Frank

Hello Frank-san

Thank you for quick response.

I got  waveform of replaced 22Ω to 0Ω.

This waveform is confirmed at CMD line only.(DATA and CLK line is normal)

And I answer your question as follows.

If there are any questions, please let me know.

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could you please share the scope-plot with the 22Ohm series-resistors replaced by 0-Ohm?

→I send waveform and scope-plot point.(see attached file)

In the XLS-file you had shown the unstable input signal: I understand that this is driven by the SoC?

→yes, unstable　signal is driven by the SOC.

Please check the drive capability of the SoC on its output. 

→OK,I'm confirming it.

You refer to FPC and TFT board, please clarify which connections are those (Input to TWL1200 or output of TWL1200)?

→FPC and TFT is output of TWL1200.

Furthermore, I think I misread the statement "it is short between SD connector and FPC": You actually refer to a short line-length between SD and FPC?

→Actually they short line-length in previous,but  they replace 22 ohm to 0 ohm  in this file.

Please check the parasitic capacitance of the "long" connection (Is this board-trace or cable?).

→The value in previous file  is the all capacitance value including the cable.(The input capacity is excluded)

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Regards

Tomohiro Nagasawa

Waveform of TWL1200 (22Ω→0Ω）.xlsx

Nagasawa-san,

The waveforms in the latest file seem to be acceptable:

The input signal is clean (did they do anything to make sure it does not have the low-pulse right after ramp-up?).

The output has some ringing, but at these switching speeds some ringing is to be expected (In fact, some of it may also be artificial and introduced by a GND-loop of the probe-head. How and where did you connect the GND-lead of the probe-head for both probes? If a nearby GND is available, a "Walking-stick-grounding" is highly preferred ofver the classical GND-clamp).

Could you please find out about the lenght and dimensions of the board/trace/cable or simulate the capacitive loading of both, the original line-lenght (FPC-board plus connectors and traces on other boards) and the reduced line-length? You refer to the previous file, but it only reads <75pF. Is this confirmed including all contributors and much is it?

Many thanks,

Frank

Hello Frank-san

Thank you for very quick response.

They are trying to improve dull edge of CMD output. (See attached new waveform)

And drive capacity of SOC is 2mA.

I guess that this issue is caused by not enough ability for drive of SoC,and changing of the open-drain and push-pull is not work well.

■Question

①Could you advice about  the reason to become such a dull waveform in waveform1 and solution?

②Please teach the condition that the TWL1200-Q1 output of CMD line changes Open drain  to Push pull?

③Could you advise about the reason why waveform changes in waveform3?

■Answer

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The input signal is clean (did they do anything to make sure it does not have the low-pulse right after ramp-up?).

→They just replace 22Ω to 0Ω.

The output has some ringing, but at these switching speeds some ringing is to be expected (In fact, some of it may also be artificial and introduced by a GND-loop of the probe-head. How and where did you connect the GND-lead of the probe-head for both probes? If a nearby GND is available, a "Walking-stick-grounding" is highly preferred ofver the classical GND-clamp).

→OK, I will check this.

Could you please find out about the lenght and dimensions of the board/trace/cable or simulate the capacitive loading of both, the original line-lenght (FPC-board plus connectors and traces on other boards) and the reduced line-length?You refer to the previous file, but it only reads <75pF. Is this confirmed including all contributors and much is it?

→Value of previous file is measured value. I'm asking them to simulate it.

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Regards

Tomohiro Nagasawa

Waveform(R=22Ω,100Ω）.xlsx

■Question

①Could you advice about  the reason to become such a dull waveform in waveform1 and solution?

This is, as previously stated, due to a heavy loading. The edges are e-function shapes. As suggested, remove the series resistors and accept a little bit of ringing.

②Please teach the condition that the TWL1200-Q1 output of CMD line changes Open drain  to Push pull?

Please see Layout guidelines (): this is detected internally and switched automatically. Please also see the advise to limit capacitance and not use connectors:

Another issue with heavy capacitive loading has to do with the design architecture of the TWL1200's
semi-buffered, switch-type translation paths. For these I/Os, the dc drive is provided by internal pullup
resistors in combination with the open-drain or push-pull drivers that are interfaced with the TWL1200. The
ac drive, however, is provided by edge-acceleration circuitry that temporarily decreases the output
impedance of the TWL1200 SDIO lines to achieve faster output rise and fall times. When excessive
capacitance is present on these lines, the edge-acceleration circuitry times out and switches off before the
SDIO output transition is fully completed. As the SDIO output signals are reflected back to the TWL1200,
they see a higher impedance than before, causing signal reflections which can lead to glitches, ringing, or
other troublesome oscillations. Overall, layout designers should avoid use of discrete loads or connectors
on the SDIO lines where possible to keep capacitance low and manageable.

③Could you advise about the reason why waveform changes in waveform3?

At a lower switching speed there is more time to "charge" the line. I expect if you'd zoom into the edges of the 400kHz signals, you will see a degradation as well.

Hello Frank-san

We appreciate your strong support.

They are trying to review a pattern layout and position of TWL1200-Q1.

Regards

Tomohiro Nagasawa

Hello Frank-san

They try to change pattern and  reduce load capacitance of  SD connector side.(see attached file.)

But CMD line goes up only to 2.6V,(about 3.3V is expected ) does it  normally work or is there other cause?

Is  pull-up resistance effective if this works abnormally?

Could you give  reccommended pattern?

Waveform and pattern(revised)_15_02_25.pptx

Regards

Tomohiro Nagasawa

Hello Frank,

I'm Shimada TIJ FAE. Could you please reply to the previous Nagasawa-san's post? We need to solve this issue immediately.
And can you simulate to see it working correctly on your bench because they are suspecting our device has some problem?

Thanks for your support and best regards,
Kaz Shimada

Shimada-san,

Could external pull-up resistor be added on B side CMD I/O? As mentioned, the root cause could be larger load. If external pull-up resistor can be added, low-to-high driver current will increase.

BR,

Frank