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TPS3820-50-Q1 Question

Derek Xie
Genius 12255 points

Hi Team:

Just double confirm with you, if this part always no WDI signal. And the voltage is right. What the reset pin will be?

My understand is that, the reset will be like this.

On time is Ttout and off is Td. Right?

  • 0
    TI__Mastermind 27780 points
    The appropriate Applications Engineer has been assigned to respond accordingly. Thank you for your patience.
  • 0
    TI__Genius 16030 points
    Hi Derek,

    It depends on what you mean by "no watchdog signal". If WDI is floating (high-impedance), then reset will be high. If WDI is low (GND), then after Ttout the RESET pin will go low. This is the maximum on time of the PWM signal, it's best to design the PWM signal to be high for shorter than Ttout to allow some margin.

    Td is the delay time from the device going out of reset and the RESET signal actually going high. In the example you show, after a reset event, the device will wait for time Td before it releases the RESET pin high and starts the watchdog timer again.

    Regards,
    Karl
  • 0 in reply to Karl Wallinger
    TI__Genius 12255 points

    Karl：

    Thanks for your answer.

    My understand is below:

    If WDI is high -Z, the reset will keep high.

    If WDI is connect to GND, the reset will repeat high and low or just from high to low once?

  • 0 in reply to Derek Xie
    TI__Genius 12255 points

    I see the Delay and Time Out Timing Diagram, IF no WDI, the reset will be from low to high

  • 0 in reply to Derek Xie
    TI__Genius 16030 points
    Hi Derek,

    If WDI is GND, then RESET should switch between high and low repeatedly. After RESET goes low due to a watchdog timeout, it will go high again after Td, as shown in the diagram you listed. Then it will go low again after the timeout, if there is no transition on the WDI pin.

    Your are right that if WDI is high-Z, then the watchdog will be disabled, and RESET will only be a function of the sense voltage.

    Regards,
    Karl