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Replace 16-bit NAND to 8-bit NAND on DM816x EVM

Expert 2285 points

Replies: 8

Views: 3296

Hi, all!

I have DM816x EVM with 16-bit Micron NAND.

If I change it on another 8-bit Micron NAND, what I must change in u-boot?

In u-boot I modified only ./board/ti/ti8168/evm.c

board_init()
{

  ....

 gpmc_set_cs_buswidth(0, 0);
}

On DM816x EVM replace U24 from 16-bit NAND on the 8-bit NAND, and burn u-boot image from CCS. u-boot was started and detect NAND device.

 

From CCS debugger detect flash parameters:

  • [CortexA8]   NAND FLASH DETAILS
  • [CortexA8] ----------------------
  • [CortexA8]  Device ID : 0xda
  • [CortexA8]  Manufacture ID : 0x2c
  • [CortexA8]  Page Size : 2048 Bytes
  • [CortexA8]  Spare Size : 64 Bytes
  • [CortexA8]  Pages_Per_Block : 64
  • [CortexA8]  Number_of_Blocks : 2048
  • [CortexA8]  Device_width : 1 Byte
  • [CortexA8]  DeviceSize : 256 MB

 

EMV console output:

  • TI8168-GP rev 1.1
  • ARM clk: 987MHz
  • DDR clk: 796MHz
  • I2C:   ready
  • DRAM:  2 GiB
  • NAND:  HW ECC Hamming Code selected
  • 256 MiB
  • *** Warning - bad CRC or NAND, using default environment
It is enough for using NAND 8-bit NAND? Or I need change something else?
Thank you.
P.S. Sorry - my English is not very well.
  • idle,

    Kindly find attached the code variations required to select between 16 bit and 8 bit Nand. Based on the CS0BW switch on the board, this code selects the required buswidth.

    Regards,

    Parth0207.nand BW patch.txt

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  • In reply to Parth Saxena:

    Hi Parth Saxena!

    Thank you for your answer. It was very useful for me. I look into my PSP and see that it have all function from patch. I was need only to switch off CS0BW on EVM :) Thank you again.

  • In reply to Parth Saxena:

    Note:

    This patch may be a posible problem for custom boards.

    Level on CSB0BW pin defines GPMC bus width (from datasheet, CONTROL_STATUS register):

    BW: GPMC CS0 Default Bus Width, from CS0BW pin.

    0: 8-bit data bus.

    1: 16-bit data bus.

    ... but the patch redefines this to (copied from the patch):

     ti81xx: nand: add 8/16 bit nand runtime detection

    This patch adds runtime detection between 8 and 16 bit nand.
    If the BTMODE BW pin on the board is set to 0, 16-bit nand is selected.
    If the BTMODE BW pin on the board is set to 1, 8-bit nand is selected.

    Please, correct me if I am wrong.

  • In reply to Robert F.:

    Hi, Robert! 

    Yes. You are right! At this moment I encountered this problem on my custom board. And I was set +3.3V on CS0BW pin instead 0V.

    Thank you for attention.

  • In reply to Vladimir Karakozov:

    yeah, I have spent half day to figuring out why the uBoot from latest EZSDK doesn't boot.

    I tested u-boot.bin in DDR memory and it came up with:

    NAND bus width 8 instead 16 bit

    Moving CS0BW from pull up to pull down fixed the issue.

  • In reply to Robert F.:

    Yes, we had used the CS0BW switch the other way round for 8/16 bit NAND detection. This was done to maintain backward compatibility with our previous releases. Since we came across a of doubts for not using this switch as per it's documentation, we decided to rectify out code. From our upcoming release onwards, CS0BW pin should be turned OFF for 8-bit NAND and ON for 16-bit NAND (this would also be mentioned in our Release Notes).

    Regards,

    Parth

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  • In reply to Parth Saxena:

    Thank you Parth.

    Please, do you know when the new release will be available?

    BTW: I was surprised to see the 16bit memory booting up when after reset the CS0BW is set to 8bits.

  • In reply to Robert F.:

    Robert,

    The release is currently in it's testing phase. Fot the latest code, you can visit the Arago tree <http://arago-project.org/git/projects/?p=linux-omap3.git;a=summary>. Our latest release version is "04.04.00.01".

    The patch changing the CS0BW functionality in accordance with the TRM documentation can be found here:

    <http://arago-project.org/git/projects/?p=linux-omap3.git;a=commit;h=3064bce8324f67a6ac64b97ddf89e92b8aaf22b3>

    Regards,

    Parth

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