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Replace 16-bit NAND to 8-bit NAND on DM816x EVM

Hi, all!

I have DM816x EVM with 16-bit Micron NAND.

If I change it on another 8-bit Micron NAND, what I must change in u-boot?

In u-boot I modified only ./board/ti/ti8168/evm.c

board_init()
{

  ....

 gpmc_set_cs_buswidth(0, 0);
}

On DM816x EVM replace U24 from 16-bit NAND on the 8-bit NAND, and burn u-boot image from CCS. u-boot was started and detect NAND device.

 

From CCS debugger detect flash parameters:

  • [CortexA8]   NAND FLASH DETAILS
  • [CortexA8] ----------------------
  • [CortexA8]  Device ID : 0xda
  • [CortexA8]  Manufacture ID : 0x2c
  • [CortexA8]  Page Size : 2048 Bytes
  • [CortexA8]  Spare Size : 64 Bytes
  • [CortexA8]  Pages_Per_Block : 64
  • [CortexA8]  Number_of_Blocks : 2048
  • [CortexA8]  Device_width : 1 Byte
  • [CortexA8]  DeviceSize : 256 MB

 

EMV console output:

  • TI8168-GP rev 1.1
  • ARM clk: 987MHz
  • DDR clk: 796MHz
  • I2C:   ready
  • DRAM:  2 GiB
  • NAND:  HW ECC Hamming Code selected
  • 256 MiB
  • *** Warning - bad CRC or NAND, using default environment
It is enough for using NAND 8-bit NAND? Or I need change something else?
Thank you.
P.S. Sorry - my English is not very well.
  • idle,

    Kindly find attached the code variations required to select between 16 bit and 8 bit Nand. Based on the CS0BW switch on the board, this code selects the required buswidth.

    Regards,

    Parth

    0207.nand BW patch.txt
    commit 878b311ae687cb3e9f909d0f3578ce4cc674e4e6
    Author: Saxena, Parth <parth.saxena@ti.com>
    Date:   Fri Jul 29 17:15:54 2011 +0530
    
        ti81xx: nand: add 8/16 bit nand runtime detection
    
        This patch adds runtime detection between 8 and 16 bit nand.
        If the BTMODE BW pin on the board is set to 0,
        16-bit nand is selected.
        If the BTMODE BW pin on the board is set to 1,
        8-bit nand is selected.
    
        Signed-off-by: Saxena, Parth <parth.saxena@ti.com>
    
    diff --git a/arch/arm/cpu/arm_cortexa8/ti81xx/mem.c b/arch/arm/cpu/arm_cortexa8/ti81xx/mem.c
    index 3f4895a..f70a160 100644
    --- a/arch/arm/cpu/arm_cortexa8/ti81xx/mem.c
    +++ b/arch/arm/cpu/arm_cortexa8/ti81xx/mem.c
    @@ -78,6 +78,26 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
            sdelay(2000);
     }
    
    +/* gpmc_set_cs_buswidth(): Set bus width for the the specified chip select
    + * cs: GPMC chip select
    + * bw: 0=8-bit, 1=16-bit, 2=32-bit
    + */
    +void gpmc_set_cs_buswidth(u32 cs, u32 bw)
    +{
    +       u32 config1;
    +       struct gpmc_cs *cfg;
    +
    +       gpmc_cfg = (struct gpmc *)GPMC_BASE;
    +       cfg = (struct gpmc_cs *)(&gpmc_cfg->cs[cs]);
    +
    +       config1 = readl(&cfg->config1);
    +
    +       /* clear and set device size bits (13:12) */
    +       config1 &= (~0x00003000);
    +       config1 |= (bw << 12);
    +       writel(config1, &cfg->config1);
    +}
    +
     /*****************************************************
      * gpmc_init(): init gpmc bus
      * Init GPMC for x16, MuxMode (SDRAM in x32).
    diff --git a/arch/arm/cpu/arm_cortexa8/ti81xx/sys_info.c b/arch/arm/cpu/arm_cortexa8/ti81xx/sys_info.c
    index 5aa928e..c5278db 100644
    --- a/arch/arm/cpu/arm_cortexa8/ti81xx/sys_info.c
    +++ b/arch/arm/cpu/arm_cortexa8/ti81xx/sys_info.c
    @@ -125,6 +125,20 @@ u32 pg_val_ti814x(u32 pg1_val, u32 pg2_val)
                    return pg1_val;
     }
    
    +/************************************************************
    + * get_sysboot_bw(void) - return buswidth from CONTROL_STATUS
    + ************************************************************/
    +u32 get_sysboot_bw(void)
    +{
    +       int bw;
    +       bw = __raw_readl(CONTROL_STATUS) & (SYSBOOT_BW_MASK);
    +       bw >>= SYSBOOT_BW_POS;
    +       if (bw == 0)    /* 8-bit nand if BTMODE BW pin on board is ON */
    +               return 1;
    +       else if (bw == 1)/* 16-bit nand if BTMODE BW pin on board is OFF */
    +               return 0;
    +}
    +
     #ifdef CONFIG_DISPLAY_CPUINFO
     /**
      * Print CPU information
    diff --git a/arch/arm/include/asm/arch-ti81xx/cpu.h b/arch/arm/include/asm/arch-ti81xx/cpu.h
    index 7cc2988..1c8b6a1 100644
    --- a/arch/arm/include/asm/arch-ti81xx/cpu.h
    +++ b/arch/arm/include/asm/arch-ti81xx/cpu.h
    @@ -64,6 +64,10 @@
     /* This gives the status of the boot mode pins on the evm */
     #define SYSBOOT_MASK                   (BIT(0) | BIT(1) | BIT(2) |BIT(3) |BIT(4))
    
    +/* This gives the buswidth of the booting device */
    +#define SYSBOOT_BW_POS         (16)
    +#define SYSBOOT_BW_MASK                (BIT(SYSBOOT_BW_POS))
    +
     /* Reset control */
     #define PRM_DEVICE_RSTCTRL             (PRCM_BASE + 0x00A0)
    
    diff --git a/arch/arm/include/asm/arch-ti81xx/sys_proto.h b/arch/arm/include/asm/arch-ti81xx/sys_proto.h
    index 601b157..c4f634c 100644
    --- a/arch/arm/include/asm/arch-ti81xx/sys_proto.h
    +++ b/arch/arm/include/asm/arch-ti81xx/sys_proto.h
    @@ -41,11 +41,13 @@ enum cpu_rev {
     void prcm_init(u32);
     void per_clocks_enable(void);
     void gpmc_init(void);
    +void gpmc_set_cs_buswidth(u32, u32);
     void watchdog_init(void);
     void set_muxconf_regs(void);
     u32 get_cpu_rev(void);
     u32 get_mem_type(void);
     u32 get_sysboot_value(void);
    +u32 get_sysboot_bw(void);
     int print_cpuinfo (void);
     u32 is_gpmc_muxed(void);
     u32 get_gpmc0_type(void);
    diff --git a/board/ti/ti8168/evm.c b/board/ti/ti8168/evm.c
    index 9fe884d..1cacba4 100644
    --- a/board/ti/ti8168/evm.c
    +++ b/board/ti/ti8168/evm.c
    @@ -181,6 +181,18 @@ int board_init(void)
    
            gpmc_init();
    
    +       /* GPMC will come up with default buswidth configuration,
    +    * we will override it based on BW pin CONFIG_STATUS register.
    +    * This is currently required only for NAND/NOR to
    +    * support 8/16 bit NAND/NOR part. Also we always use chipselect 0
    +    * for NAND/NOR boot.
    +    *
    +    * NOTE: This code is DM8168 EVM specific, hence we are using CS 0.
    +    * Also, even for other boot modes user is expected to
    +    * on/off the BW pin on the EVM.
    +    */
    +       gpmc_set_cs_buswidth(0, get_sysboot_bw());
    +
            return 0;
     }
    

  • Hi Parth Saxena!

    Thank you for your answer. It was very useful for me. I look into my PSP and see that it have all function from patch. I was need only to switch off CS0BW on EVM :) Thank you again.

  • Note:

    This patch may be a posible problem for custom boards.

    Level on CSB0BW pin defines GPMC bus width (from datasheet, CONTROL_STATUS register):

    BW: GPMC CS0 Default Bus Width, from CS0BW pin.

    0: 8-bit data bus.

    1: 16-bit data bus.

    ... but the patch redefines this to (copied from the patch):

     ti81xx: nand: add 8/16 bit nand runtime detection

    This patch adds runtime detection between 8 and 16 bit nand.
    If the BTMODE BW pin on the board is set to 0, 16-bit nand is selected.
    If the BTMODE BW pin on the board is set to 1, 8-bit nand is selected.

    Please, correct me if I am wrong.

  • Hi, Robert! 

    Yes. You are right! At this moment I encountered this problem on my custom board. And I was set +3.3V on CS0BW pin instead 0V.

    Thank you for attention.

  • yeah, I have spent half day to figuring out why the uBoot from latest EZSDK doesn't boot.

    I tested u-boot.bin in DDR memory and it came up with:

    NAND bus width 8 instead 16 bit

    Moving CS0BW from pull up to pull down fixed the issue.

  • Yes, we had used the CS0BW switch the other way round for 8/16 bit NAND detection. This was done to maintain backward compatibility with our previous releases. Since we came across a of doubts for not using this switch as per it's documentation, we decided to rectify out code. From our upcoming release onwards, CS0BW pin should be turned OFF for 8-bit NAND and ON for 16-bit NAND (this would also be mentioned in our Release Notes).

    Regards,

    Parth

  • Thank you Parth.

    Please, do you know when the new release will be available?

    BTW: I was surprised to see the 16bit memory booting up when after reset the CS0BW is set to 8bits.

  • Robert,

    The release is currently in it's testing phase. Fot the latest code, you can visit the Arago tree <http://arago-project.org/git/projects/?p=linux-omap3.git;a=summary>. Our latest release version is "04.04.00.01".

    The patch changing the CS0BW functionality in accordance with the TRM documentation can be found here:

    <http://arago-project.org/git/projects/?p=linux-omap3.git;a=commit;h=3064bce8324f67a6ac64b97ddf89e92b8aaf22b3>

    Regards,

    Parth