Hello,
I am using the MSP430F5436A on the MSP-EXP430F5436A with the CC2500 mounted on RF1+RF2.
I am using the example code (MSP430 Interface to CC1100/CC2500 Code Library, Associated code files) and i want to increase the SPI CLK.
The datasheet says the maximum CLK is 6MHz.
In the example program , SMCLK is set (by default) to 1MHz.
at the SPI initialization, the SPI CLK is set to SMCLK/2=500KHz:
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
UCB0CTL1 |= UCSWRST; // **Disable USCI state machine**
UCB0CTL0 |= UCMST+UCCKPH+UCMSB+UCSYNC; // 3-pin, 8-bit SPI master
UCB0CTL1 |= UCSSEL_2; // SMCLK
UCB0BR0 = 0x02; // UCLK/2
UCB0BR1 = 0;
TI_CC_SPI_USCIB0_PxSEL |= TI_CC_SPI_USCIB0_SIMO
| TI_CC_SPI_USCIB0_SOMI
| TI_CC_SPI_USCIB0_UCLK;
// SPI option select
TI_CC_SPI_USCIB0_PxDIR |= TI_CC_SPI_USCIB0_SIMO | TI_CC_SPI_USCIB0_UCLK;
// SPI TXD out direction
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
}
For easy debug, i configured time B to interrupt every 255*4000 = 1.02*10^6 MCLK counts.(1.02Sec for MCLK=1MHz, and 255msec for MCLK=4MHz)
Every time timer B interrupts i send a signal - causing the other board that runs the example app to blink it's LED:
#pragma vector=TIMERB1_VECTOR
__interrupt void TIMERB1_ISR(void)
{
counter += 1;
if(counter>4000)
{
// Build packet
txBuffer[0] = 2; // Packet length
txBuffer[1] = 0x01; // Packet address
txBuffer[2] = BIT0; // Load switch inputs
RFSendPacket(txBuffer, 3); // Send value over RF
__delay_cycles(100000); // Switch debounce
TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN; // Clear GDO flag
TI_CC_SW_PxIFG &= ~(TI_CC_SW1+TI_CC_SW2); // Clr flag that caused int
// Clear it.
counter = 0;
}
}
When i don't change the MCLK, the program works - the other board's LED is blinking.
Whenever i change the MCLK, say to 4MHz, with the following code, the program stops working, although i think i send the signal, nothing get received at the other side - thefore the LED doesn't blink.
void SetVcoreUp (unsigned int level)
{
// Open PMM registers for write
PMMCTL0_H = PMMPW_H;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}
//*****************************************************************************
//
//! initClk
//!
//! @param None
//!
//! @return none
//!
//! @brief Init the device with 25 MHz DCOCLCK.
//
//*****************************************************************************
void initClk(void)
{
SetVcoreUp (PMMCOREV_1); //Increase slowly Vcore
SetVcoreUp (PMMCOREV_2); //Increase slowly Vcore
SetVcoreUp (PMMCOREV_3); //Increase slowly Vcore to work with DCO = 25MHz
P11DIR |= BIT0 | BIT1 | BIT2; // Set pin 11.0,11.1,11.2 to output ACLK, MCLK, SMCLK
P11SEL |= BIT0 | BIT1 | BIT2; // Select pin 11.0,11.1,11.2 to output ACLK, MCLK, SMCLK
UCSCTL3 = SELREF__REFOCLK; // select REFO as FLL source
UCSCTL6 = XT1OFF | XT2OFF; // turn off XT1 and XT2
/* Initialize DCO to 4.00MHz */
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x1f<<8; // Set DCOx=31, MODx=0
UCSCTL1 = DCORSEL_2 ; // Set DCORSELx for DCO = 3.17 MHz - 7.38 MHz
UCSCTL2 = 121u; // Set DCO Multiplier for 4MHz
// (N + 1) * FLLRef = Fdco
// (121 + 1) * 32768 = 4MHz
UCSCTL4 = SELA__REFOCLK | SELS__DCOCLK | SELM__DCOCLK;
// Select Aclock = REF0CLK
// Select SMclock = DCOCLK
// Select Mclock = DCOCLK
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32*32*4MHz/32768Hz = 125000 = MCLK cycles for DCO to settle
__delay_cycles(125000u);
/* Loop until XT1,XT2 & DCO fault flag is cleared */
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}
while (SFRIFG1&OFIFG); // Test oscillator fault flag
}
Any ideas what is wrong?
Thanks.