Hello,
I have to use some part of CORE0_L2_SRAM as cache. Please check the modified 6678.cmd file.
CORE0_L2_SRAM: o = 0x10800000 l = 0x00040000 /* 256kB CORE0 L2/SRAM */
CORE0_L2_CACHE: o = 0x10840000 l = 0x00040000 /* 256kB CORE0 L2/CACHE */
CORE0_L1P_SRAM: o = 0x10E00000 l = 0x00008000 /* 32kB CORE0 L1P/SRAM */
CORE0_L1D_SRAM: o = 0x10F00000 l = 0x00008000 /* 32kB CORE0 L1D/SRAM */
CORE1_L2_SRAM: o = 0x11800000 l = 0x00080000 /* 512kB CORE1 L2/SRAM */
CORE1_L1P_SRAM: o = 0x11E00000 l = 0x00008000 /* 32kB CORE1 L1P/SRAM */
CORE1_L1D_SRAM: o = 0x11F00000 l = 0x00008000 /* 32kB CORE1 L1D/SRAM */
CORE2_L2_SRAM: o = 0x12800000 l = 0x00080000 /* 512kB CORE2 L2/SRAM */
CORE2_L1P_SRAM: o = 0x12E00000 l = 0x00008000 /* 32kB CORE2 L1P/SRAM */
.........................
. .........................
SECTIONS
{
#ifdef CORE0
.text > CORE0_L2_SRAM
.stack > CORE0_L2_SRAM
.bss > CORE0_DDR3 /*CORE0_L2_SRAM*/
.cio > CORE0_L2_SRAM
.const > CORE0_L2_SRAM
.data > CORE0_DDR3 /*CORE0_L2_SRAM*/
.switch > CORE0_L2_SRAM
.sysmem > CORE0_L2_SRAM
.far > CORE0_L2_SRAM
.args > CORE0_L2_SRAM
.ppinfo > CORE0_L2_SRAM
.ppdata > CORE0_L2_SRAM
/* COFF sections */
.pinit > CORE0_L2_SRAM
.cinit > CORE0_L2_SRAM
/* EABI sections */
.binit > CORE0_L2_SRAM
.init_array > CORE0_L2_SRAM
.neardata > CORE0_L2_SRAM
.fardata > CORE0_L2_SRAM
.rodata > CORE0_L2_SRAM
.c6xabi.exidx > CORE0_L2_SRAM
.c6xabi.extab > CORE0_L2_SRAM
/* CACHE section */
.external > CORE0_L2_CACHE
#endif
Also enabled caching using CSL functions in code.
#pragma DATA_SECTION(TempOut1,".external")
float TempOut1[2048][2140][3];
#pragma DATA_SECTION(TempOut,".external")
float TempOut[2048][2140][3];
int main(int argc, char **argv)
{
CACHE_L2Size size;
CACHE_enableCaching(256);
CACHE_setL2Size(CACHE_256KCACHE);
...
}
AT the time of execution we can see from memory map usage for cache is 0%. I did not get why code is not using defined cache.
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
SHRAM 0c000000 00400000 000071e7 003f8e19 RWIX
CORE0_L2_SRAM 10800000 00040000 00000000 00040000 RWIX
CORE0_L2_CACHE 10840000 00040000 00000000 00040000 RWIX
CORE0_L1P_SRAM 10e00000 00008000 00000000 00008000 RWIX
CORE0_L1D_SRAM 10f00000 00008000 00000000 00008000 RWIX
CORE1_L2_SRAM 11800000 00080000 00000000 00080000 RWIX
Where I missed anything? The linker file used C6678.cmd is correct ?
Is there any other linker file for K2H? Please advise thanks in advance.