I'm planning to have the FPGA that is powered from these POLs set the sync, however this statement in the datasheet is concerning, because the FPGA longer than 20 us to come up.
In external synchronization mode, a resistor is connected between the RT pin and GND. The Sync pin requires a
toggling signal for this mode to be effective. The switching frequency of the device goes 1:1 with that of Sync pin.
External system clock-user supplied sync clock signal determines the switching frequency. If no external clock
signal is detected for 20 μs, then TPS50601-SP transitions to its internal clock, which is typically 500 kHz.
Does this mean it permanently used the internal clock, or will it transition back to a sync clock if one is provided?
Thanks
