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SM320F2812-EP: current shipping silicon revision + RAM block question

BillyO
Genius 17555 points
Part Number: SM320F2812-EP
Other Parts Discussed in Thread: SM320F2812

Hi team,

 

Can someone let me know what silicon revision of the SM320F2812PGFMEP we’re shipping?

 

Per the errata the latest is G, the only other reasonable possibility is E.

http://www.ti.com/lit/er/sprz193q/sprz193q.pdf

 

[Edit] - Also can you tell me if the L0 and L1 blocks of RAM are useable? Also the H0 block?

Thanks,

Billy

  • 0
    TI__Guru 62930 points

    Billy, SM320F2812-EP is using rev G.

    This should also be evident on the device symbolization.

         +-----------------+                                                          

         |   TI      DSP   |     YMLLLLS = LOT TRACE CODE                            

         |   BUG           |     YM      = 2 DIGIT YR/MO DATECODE                    

         |   SM320F2812    |               UPDATED MONTHLY                            

         |   GHHMEP        |     LLLL    = ASSY LOT                                  

         |   $#-YMLLLLS    |     S       = ASSY SITE CODE                            

         |O                |     $       = WAFER FAB CODE                            

          \----------------+     #       = DIE REV CODE(Major Rev Only)              

        O = PIN ONE LOCATION                  

    With respect to the question on the SARAMs.

    Datasheet page 34.

    3.2.9 L0, L1, H0 SARAMs
    The F281x and C281x contain an additional 16K x 16 of single-access RAM, divided into 3 blocks
    (4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is
    mapped to both program and data space.

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade

  • 0 in reply to Wade Vonbergen
    TI__Genius 17555 points
    Thanks Wade,

    If they had the device you're right I would have easily known this but they were asking presales. Thanks for pointing out the RAM section I missed.

    Thanks,
    Billy