Hi
can you explain the working of SN54196 IC?
Why there are 3 inputs for divide by 5 counter? Can the IC divide 3 frequencies simultaneously?
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Hi
can you explain the working of SN54196 IC?
Why there are 3 inputs for divide by 5 counter? Can the IC divide 3 frequencies simultaneously?
Ayovi,
The 54196 has two counters (2 clocks); one divides by 2 the other by 5.
The Load and CLR affect both counters.
It can divide 2 frequencies simultaneously.
can you please say then why are there 3 inputs and 3 outputs for the divide by 5 counter..
There are 2 clk inputs, 4 count inputs (ABCD), 1 CLR input, 1 LOADn input, and 4 outputs Q(ABCD).
This device was released in 1976, and there is little additional data on operation.
I suspect the 3 outputs are the 3 bits of the encoded quinary counter.
See Wikipedia article on bi-quinary counters.
Regards,
Wade