The application intends to make use of SN&$V263 FIFO, where 9 bits wide input and output buses are used. And the "writes' after which the FIFO will assert the Full Flag is 16384. The "half full" flag will be asserted at 8193rd write.
At the time when this half flag is asserted, the contents of the FIFO will be read Continuously without any break and thus making the writing and reading operation, a continuous one.(There will be writing and reading going on side by side, thus ensuring the full flag is nor asserted at any point of time)
Now, there will be some point of time when the last location of the FIFO will be written. After this last location is written, will the write pointer automatically points to the first memory location and continues to write? (As in the case of circular FIFO). Will there be any extra time delays for the pointer to point from the last memory location to the first memory location? If so, what will be the delay?
