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ADS4245-EP: Setup and hold time at 15MSPS

Mahesh KC03
Intellectual 1360 points
Other Parts Discussed in Thread: ADS4245-EP

Hi,

One of my customers is using the ADS4245-EP in a parallel CMOS output format at 15Msps. The datasheet mentions the output setup and hold time on the parallel interface starting from 65Msps in Table 3 on page 15. Since this application is at 15Msps, can I extrapolate the data from the list as setup time to be 40% of T and hold time to be 42% of T and arrive at 26ns rise and 28ns hold time?

Is there actual data available?

  • 0
    TI__Guru 62930 points
    Mahesh,
    The data should be transitioning based on the falling edge timing of CLKOUT, giving the largest window to rising edge of CLKOUT externally.
    My interpretation would be that the delays from CLKOUT falling should essentially remain the same regardless of frequency.
    I took a look at the setup/holds across frequency, and this relationship is true, with some additional margin at lower frequencies.

    Using the values you have calculated would be very conservative.
    Based on using an additional 2ns guardband over the 65MSPS values, I get a setup of 30.7ns, and hold of 30.3ns.
    These are not tested values, and data does not exist at this condition to validate.

    Adding additional margin would be good.
    I am going to check with commercial team to validate my analysis, and will reply back.
    Regards,
    Wade