This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS5400-SP: ADS5400-SP and DAC5670-SP Clocking Questions

Part Number: ADS5400-SP
Other Parts Discussed in Thread: DAC5670-SP, , ADS5400

My customer has asked the following questions concerning the ADS5400-SP and DAC5670-SP:

The big question I’m unclear on is the required data rate from the FPGA. Right now we are targeting an IF / sample rate of 614.4MHz. In order for that to work with the FPGA we have selected, I’ll need to be able to interface to the devices at a div4 rate.  

From the DAC5670-SP datasheet Figure 1, it looks like the data from the FPGA uses DTCLK as a DDR clock, so that I can drive DA and DB on each edge of DTCLK at 153.6 MHz to achieve the target output frequency. One concern I have is that Table 7.8 specifies that Fdac is 1-2.4 GHz. Can we run the device at 614.4 MHz? 

For the ADC (ADS5400-SP), I’m less clear.  The single bus mode timing diagram shows a DDR type input bus, but we cannot keep up with that clock rate within the FPGA (307.2 MHz). I’d like to run the device in the dual bus, aligned, div 4 mode. I’m unclear whether that mode treats the input buses as DDR or not. 

Basically, just trying to make sure these devices have been spec’d properly. There may be time to adjust the frequency plan if they have not been, but I need to figure that out ASAP.

I believe that the slower clocking speed in the DAC5670-SP will be fine, but will it still meet or exceed the data sheet parameters?

Thanks for your help with this!

Richard Elmquist

  • With respect to the DAC5670.  The 1GHz to 2.4Ghz specification is to indicate the range that the DLL is effective.  Slower than this range, it is necessary to operate with the DLL in RESTART.   When DLL is in restart, the delays are fixed, and the timing for setup/hold should be used based on DLYCLK.

    The DAC can be operated slower than 1Ghz.   We have multiple customers sampling in the 200Mhz to 300 Mhz range.

    For the ADS5400.   There is a section in the datasheet that indicates the following:

    This is on page 37.

    Output Bus and Clock Options

    The ADS5400 has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In

    single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock

    rate on A and B. While in single bus mode, CLKOUTA will be at frequency CLKIN/2 and a DDR interface is

    achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing

    options for an SDR or DDR interface.

    This indicates that in dual bus mode, DDR can be utilized by setting CLKIN/4.



  • Wade,

    Thanks for your response!

    I will let you know if the customer has any further questions.

    Thanks again.

    Richard Elmquist