Other Parts Discussed in Thread: DAC5670-SP, , ADS5400
My customer has asked the following questions concerning the ADS5400-SP and DAC5670-SP:
The big question I’m unclear on is the required data rate from the FPGA. Right now we are targeting an IF / sample rate of 614.4MHz. In order for that to work with the FPGA we have selected, I’ll need to be able to interface to the devices at a div4 rate.
From the DAC5670-SP datasheet Figure 1, it looks like the data from the FPGA uses DTCLK as a DDR clock, so that I can drive DA and DB on each edge of DTCLK at 153.6 MHz to achieve the target output frequency. One concern I have is that Table 7.8 specifies that Fdac is 1-2.4 GHz. Can we run the device at 614.4 MHz?
For the ADC (ADS5400-SP), I’m less clear. The single bus mode timing diagram shows a DDR type input bus, but we cannot keep up with that clock rate within the FPGA (307.2 MHz). I’d like to run the device in the dual bus, aligned, div 4 mode. I’m unclear whether that mode treats the input buses as DDR or not.
Basically, just trying to make sure these devices have been spec’d properly. There may be time to adjust the frequency plan if they have not been, but I need to figure that out ASAP.
I believe that the slower clocking speed in the DAC5670-SP will be fine, but will it still meet or exceed the data sheet parameters?
Thanks for your help with this!
Richard Elmquist
