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ADC12D1600QML-SP: CLK input by CDCLVP111-SP at using AutoSync

masahiko shimizu
Guru 11235 points
Part Number: ADC12D1600QML-SP
Other Parts Discussed in Thread: CDCLVP111-SP, CDCLVP111

Hi,

My customer uses two of ADC12D1600QML-SP.
and uses AutoSync function.

Customer wants to divide the clk for two ADC for this functipn.
He thinks using CDCLVP111-SP.
I has attached file of circuit image.

Can ADC12D1600QML-SP accept the clk signal from CDCLVP111-SP as attached file circuit?

CDCLVP111-SP_ADC12D1600QML-SP.pptx


Best regards,
Shimizu

  • 0
    TI__Guru 62930 points
    Shimizu,
    First off, there is a typo in the Vin_clk row. The square wave clock should show 0.4V minimum, not 0.04V.
    The CDCLVP111-SP when properly biased should be able to provide good clocking for the ADC. Your block diagram looks good.
    I would recommend validating with IBIS simulation.

    The 350mv will provide minimum of 700mv pk-pk.
    Regards,
    Wade