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SN74V273-EP: No output after confirmed write cycle

Nicholas Strong
Prodigy 20 points

Part Number: SN74V273-EP

Hello,

I am a Computer Engineering Junior and am currently working on a design team working to build a cubesat that is set to launch in 2019.

We are currently working to make two SN74V273-EP memory chips working on a board we have fabricated.We can currently fill up the FIFO (Empty Flag deasserts and Full Flag asserts). The problem that we run into is that we cannot get any output. We have verified the Read and Write clocks, and have verified that we are asserting the Read Enable and Output Enable correctly and with correct timing. The issue is that we are not getting any output from either chip nor any feedback from the Full Flag indicating that we are reading out.

We are writing to the FIFOs using the Flexbus module on a Kinetis microcontroller and controlling the FIFO flags using a Max II CPLD.

I have attached the datasheet and oscilloscope screenshots of read and write cycles below.

Thank you for your time and if any more details are needed I will be respond back as soon as I can.

Write Cycle 40us:

Write Cycle 1us:

Read Cycle 40us (as you can see Q[0] is giving no output once clocked):

Read Cycle .4us: :

sn74v273-ep.pdf

  • 0
    TI__Guru 62930 points
    Nicholas,
    I can try to help.
    A couple comments. Your plots seems to show that OE is not driven adequately. The high level appears to be less that 2V.
    The minimum VIH level is 2V for this device. (This may or may not be the only issue).

    Also, a common stumbling block with this family of devices is the failure to properly assert the master reset after power up.
    There is a timing diagram in figure 5. Note, that MRS must drive high, then low, then high again. The first falling edge of MRS has timing requirements to it, and also to its falling edge. Note requirements for TRSS, TRSR, and TRSF.
    Can you confirm that the reset is properly asserted? It can cause erroneous behavior.
    Also confirm proper drive levels.

    Your write clock does not appear very clean, but possibly this is artifact of the probe you are using.

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    Prodigy 20 points
    Thanks Wade.

    Just letting you know I've read this. We are investigating what you pointed out and will reply with more information if nothing is resolved.