SMV320C6727B-SP: Power-Rail Sequencing and De-Sequencing

For the C6727B, there is a paragraph in the datasheet regarding this:

4.7.1 Power-Supply Sequencing

This device does not require specific power-up sequencing between the DVDD and CVDD voltage rails;

however, there are some considerations that the system designer should take into account:

1. Neither supply should be powered up for an extended period of time (>1 second) while the other

supply is powered down.

2. The I/O buffers powered from the DVDD rail also require the CVDD rail to be powered up in order to be

controlled; therefore, an I/O pin that is supposed to be 3-stated by default may actually drive

momentarily until the CVDD rail has powered up. Systems should be evaluated to determine if there is

a possibility for contention that needs to be addressed. In most systems where both the DVDD and

CVDD supplies ramp together, as long as CVDD tracks DVDD closely, any contention is also mitigated by

the fact that the CVDD rail would reach its specified operating range well before the DVDD rail has fully

ramped.

Similarly, the C6701 has a shorter, but essentially equivalent paragraph on page 26.

Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.

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Regards,
Wade