Other Parts Discussed in Thread: ADS4245
Hi all,
We are using ADS4245 EP in our design and you can see the below schematic related to the ADC portion of the design. R268 is not mount, CTRL1 is tied to a power down signal. We are using Kintex 7 series FPGA to collect the data and the ADC clock is set to be 10 MSPS. We also tried the ADC, in offset binary CMOS mode by changing the resistor configuration in SEN pins and there is not any problem in this mode. So we make sure that there is not problem related to the CLK or analog data paths.
When we try to take LVDS DDR data, we see the below results,
0 V dc:
We really stuck at this point and any help would much appreciated,
Thanks in advance,
Ekrem.