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UC1843A-SP: Can I override the oscillator cap discharge at RT/CT?

Joerg
Prodigy 170 points
Part Number: UC1843A-SP
Other Parts Discussed in Thread: UC1843-SP, UC1843

I am planning to use the UC1843A-SP in a non-SMPS function where the frequency will be low, between 10Hz and 300Hz. Also, I need to stop the oscillator in the position where the output is low and, therefore, the RT/CT pin has to be forced to the Vref level of 5V for long periods of time. Actually, nearly all the time except for brief periods of activity. Questions, and preferably I'd need a more official answer from TI:

1. Can I use large capacitors if several uF? The datasheet stops at 100nF but that's just a graph.

2. Can I pull the RT/CT pin to VRef via a 10-30ohm resistance? This would pull the pin up against the 8.3mA discharge current, not much.

3. There is no abs max rating for the RT/CT pin. I assume Vref of 5V is ok. Correct?

4. What is the upper RT/CT pin voltage threshold where the oscillator flips into discharging the cap? The datasheet only states an amplitude of 1.7V but no upper or lower thresholds.

I know I can stop the chip via the current sense or comp pin but not in this case. The reason is that then the oscillator would keep running and will not be synchronized to our on-off signal. If I hold the RT/CT pin high the oscillator will always start in a defined state and thus the first pulse out of the chip will always be happening at the same delay. Given that I'd only be forcing against the 8.3mA discharge current I don't see any problem but since this is eventually going to fly I need an answer from TI about this.

Regards, Joerg

  • 0
    TI__Mastermind 20045 points
    Hello Joerg,

    1. The recommended capacitor range is from 1nF to 100nF. I will have to look at what we may support on the larger uF side.
    2. We recommend resistor ranges from 5k to 100k. I will also have to look what we may be able to support on the smaller side.
    3. I believe the recommended max is 5V and the absolute maximum is 6.3V. I will double check and confirm.

    While I look into these are you able to more detail your application? I'm curious what the usecase is as we may be able to help with a better solution. You also may be interested in the synchronization section (page 6) of this paper www.ti.com/.../slua110.pdf.

    Thanks,
    Kyle
  • 0 in reply to Kyle Rakos
    TI__Mastermind 20045 points
    Hello Joerg,

    I have confirmed we don't have any additional information about lower frequencies other than what I provided above. While we didn't characterize a lower frequency limit, this device was intended to operate as a PWM controller for power supplies; therefore, you may run into issues when trying to operate it outside its recommended range. We do not have data on this though.

    If you would like to detail your application I can see if we have any other suggestions to help.

    Thanks,
    Kyle
  • 0 in reply to Kyle Rakos
    Prodigy 170 points

    Hello Kyle,

    Thanks for checking with the factory about it. What we want to do is pulse a load that needs a programmable number of slow cycles at 20Hz or less. A critical parameter is that the start of this pulse sequence always happens the same number of milliseconds after a command signal goes high. That requires me to stall the oscillator instead of using the usual 1843 shut-off methods. All this has to be rad-hard which reduces my component selection to very few ICs and usually older architectures like the UC1843. I could kludge a similar funtionality from comparators, logic and all sorts of parts but would rather use your UC1843-SP because otherwise it becomes a parts paperwork issue because of the rad-hard requirement. For flight all the parts have to be vetted so we'd like to drive for a minimum, or highest possible integration.

    What I have seen in an app note and it probably was from TI was where an external signal was piped into the RT/CT pin, no capacitor at all. In other words driving it hard from a totem-polse logic output.  However, that was for the civilian version which is probably identical in that regard but I am not sure, hence my questions here. From an IC design point of view it should be possible to connect larger caps and also pull RT/CT up to Vref hard (when no pulses are commanded and the output should remain low) because there would only be the 8.5mA discharge current flowing. Unless there is another time-out in it someplace but I can't imagine that and it's not in the block diagram.

    Regards,

    Joerg

  • 0 in reply to Joerg
    TI__Mastermind 20045 points
    Hello Joerg.

    I must not have seen that app note. Do you have a link? Either way, if it worked with the commercial version, I see no reason it wouldn't work with the space version.

    Thanks,
    Kyle
  • 0 in reply to Kyle Rakos
    Prodigy 170 points
    Hello Kyle,

    It's app note SLUA143 from the old Unitrode days (the company TI bought decades ago):

    www.ti.com/.../slua143.pdf

    In figure 23 on page 3-62 they drive the RT/CT pin hard from a 555 timer chip. In our case we also need to hold RT/CT high for extended periods of time, or actually most of the time. This in order to keep the output low when no commands are issued which could be for hours, days or weeks.

    Regards,

    Joerg
  • 0 in reply to Joerg
    TI__Mastermind 20045 points
    Hello Joerg,

    After discussing with another member of my team, we don't see any glaring issues with this approach. However, since the controllers have never been tested under these conditions we are unable to definitively say.

    Thanks,
    Kyle
  • 0 in reply to Kyle Rakos
    Prodigy 170 points
    Thanks, Kyle. I'll go ahead then and design it in for ground testing. If the client needs this vetted before flight use we could revisit and maybe someone at TI could take a look at the device geometries in the 8.5mA discharge path. With this device being laid out decades ago on a fairly old process I can't see why they wouldn't be sufficiently large for such a small current.