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MSP430F249-EP: Using EMEX to divide flash segment erase cycle

Part Number: MSP430F249-EP
Other Parts Discussed in Thread: MSP430F249


I'm using a MSP430f249-EP in avionic equipment.
The embeded code have to erase a segment in the flash memory.
The flash controller freqeuncy is 333KHz, therefore the erase cycle time is about 14.5ms (4819 / 333KHz).
But during this erase cycle, the CPU have to access the flash evry 400us to write some words in other segments.
Also, it is forbidden to use interrputs in this software.

How to do that ?

The erase functional unit code could be in RAM, so it the CPU is not held.

If the sequence below (duration about 450us) is repeated 37 times (total erase time ~14.5ms) :

---> a) - start an erase cycle (segement 30)
|      b) - 400us after start, stop the flash erasing (segment 30) by setting EMEX,
|      c) - writing some words (segment 20)

Is the flash segment 30 properly erased ?



  • Frederic,

    No worries about the interrupts here as when the Flash Controller is in the process of erasing or writing the flash, interrupts are disabled. As far as using the Emergency Exit feature (EMEX), the result of an intended operation (Flash erase or write) is unpredictable. This is discussed in section 7.3.5 Stopping a Write or Erase Cycle in the family user guide.

    In short, what you have proposed above would not work as you wouldn't know if you properly erased the segment, and you would never finish erasing a segment due to the 400us interruption. You can't start back up form where you left off. Your best bet is to save the data that needs to be written to flash in RAM until the Flash sector you want to erase is complete. Then you can write to flash with multiple data points instead of one.

    This application seems perfect for some of our FRAM devices due to the memory structure of FRAM; however, I see you are using the EP version of the MSP430F249, which leads me to believe FRAM will not have the temp requirements you acquire. We do have an FRAM product that goes to 105C, but nothing to 125C in that memory type currently.
  • Thanks for your answer Jace,

    In our application, the MCU have to be "EP", and the erase cycle must be absolutely suspended for two reason :

    firstly : for saving some data every 400us => RESOLVED : save data in RAM, then writting to flash after erase cycle was completed.

    secondly : every 400us, the flash erasing must be suspended during 200us, then can be resumed for 200us, until the segment was completely erased. => sorry, but because of industrial secrecy, I can not disclose the reason.

    I thought of another strategy, using NMI interrupt & EEI, something like this :

    Erase procedure (initiated from flash, errata FLASH19 : EEI does not work with code in RAM):

    - prepare FCTL1 to erase a flash segment
    - unlock flash in FCTL3
    - set the RESET pin to NMI input, then wiring the NMI input pin on the external signal that deliver the timming information (square wave)
    - enable NMI interrupt
    - enable EEI interrupt
    - dummy write on the segment that must be erased (if i understood correctly, the controller will be interrupted by the NMI,
    then resume segment erasing after NMI was serviced, and this will be done until
    the segment was completely erased)
    - disable NMI interrupt
    - save data stored in RAM to a flash segment...
    - RET

    NMI interrupt procedure :

    - clear NMI flag
    - save data in RAM
    - waiting 200us (by polling NMI input pin)
    - enable again NMI interrupt (because automaticly disabled when enter to NMI interrupt procedure)
    - RETI

    I have tested a corresponding code and it seems to works fine.
    => The number of NMI interrutpions between enter and exit "Erase procedure" is about 38,
    => The total amount of erase time is about 14.5ms (measured with an oscilloscope on a flag I/O).

    In the family user guide (7.3.4), EEI is explained when using a maskable interrupt + GIE, but not when EEI is used whith a NMI.

    The question is : can we are absolutely sure that the segment has been properly erased, when using EEI & NMI in this way ?

    Please need answer to implement (or not) on equipment.


  • Frederic,

    Something to keep in mind here that I should of looked at earlier. Errata FLASH19, FLASH24, FLASH27, and FLASH36 are all about the Emergency Exit function of the Flash. Basically, due to the errata on this device, the EE function is really not advisable to be used. These errata basically cause code to not be properly executed in RAM, erase cycles to not be resumed, erase/write cycles to fail, and degradation of flash pages that are aborted. With these errata for this device, I would not recommend using the EE functionality.
  • Jace,

    Ok to not use the emergency exit functions, EMEX (Emergency Exit) and EEIEX (Enable Emergency Interrupt Exit).

    But i don't understand your answer about the EEI (Enable Erase Interrupt).

    On SLAU144J (p320) :

          "When EEI = 1, GIE = 1, and EEIEX = 0, a segment erase is interrupted by a pending interrupt every
           32 fFTG cycles. After servicing the interrupt, the segment erase is continued for at least 32 fFTG cycles or
            until it is complete..."

    EEI is described as a controlled function of suspend/resume of erase cycle, not as an unpredictable emergency exit.

    The errata of EEI that i found do not impact our software :

    - FLASH19 : no impact, because our code is now executed from flash.
    - FLASH27 : no impact, because NMI is used, thus interrupts will be happen regardless of GIE.

    Is the EEI secure and reliable or there are some problems with this function ?



  • Frederick,

    My apologies here. I was equating mentally EEI (Enable Erase Interrupts) with the Emergency Exit feature. The problem with too many acronyms in documentation across devices I fear. The EEI feature should work in your case as long as you are aware of and take care of the errata. Sorry for my confusion here.