I am trying to understand nandecc hw,
there is a table with column
1. hadrware error detection
2. driver solution - error correction
With omap35x for example it shows,
HW error detection support: 1(g),4 (pink?),8(g)
driver solution - 8,
1. Does driver solution here means hadware correction (not software) ?
2. How do we choose the hw error detection (between 1/4/8), or is it a feature of nand chip (and we can't change it) ?
3. if we have a chip with 4 ecc, does it means we use nand ecc 8 (driver). according to a comment in this page, this is not something good:
What will happen if an 8-bit ECC NAND is used with our 4-bit ECC capable devices?
In this scenario, if more than 4 errors are detected, the errors can't be corrected. This can have serious consequences including boot failure. It is advisable to keep correcting the ECC errors in the designated read-only/boot sections of the NAND to reduce the chances of boot failure.
4. I think the table shows that we use BCH8 only with omap35x.
So wht does there is errata with omap35x, which states "GPMC Has Incorrect ECC Computation for 4-Bit BCH Mode" ? Is it relavant ?