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SD-Card Boot Problem with OMAP4430FI1CBSR

after initializing the SD Card  switching Operation is 12 MHz, and we load data from SD Card. But it break during loading MLO to internal RAM. Around 3,5s nothing happens, but afterwards we see constantly traffic, it looks like permanent re-initializing.

it also needs long time between Output SYS_PWRON_RESET_OUT of OMAP4430 and start of I2C initializing of PMIC for SD-Card Boot. Normally it should be 4,6ms but we need 10,7ms.

We assume that the high security key (I1) is causing trouble. Is there any possibility to avoid that key or to re-Programm that security key ? In the past we used OMAP4430FCBS without any security key. We bought this lot from non-Franchise, Excess Inventory, the parts are genuine and had been factory sealed and labeled, no fake.

Thanks a lot for any good idea to solve that problem. We appreciate your gentle and fast advise.

Kind regards

Ingeborg Horn-Posmyk

AME Advanced Memory Electronics

  • Hi,

    Moving your post to right forum to be better answered.

    Thanks & regards,
    Sivaraj K
  • Hello Ingeborg,

    I think that you try to control SYS_PWRON_RESET_OUT signal by using some registers in SRCM module.
    Take a look on the listed registers in device TRM and apply the necessary changes in them.

    The power-on reset can also be asserted through software control. Software must enable the software reset assertion feature by setting the SRCM.EXTPWRONRSTCTRL[0] ENABLE bit and then by setting the SCRM.EXTPWRONRSTCTRL[1] PWRONRST bit to assert the reset.

    This routing of reset from the device pad to the PRM is enabled and disabled using the SCRM.EXTWARMRSTCTRL register. It is enabled by default.
    The status of a warm reset source for each destination is logged in the corresponding SCRM.EXTWARMRSTST_REG[0] EXTWARMRSTST bit when the destination reset is released.

    CLKSETUPTIME - This register holds the clock setup time counters of the system clock source supplier.
    PMICSETUPTIME - This register holds the setup time counters for the sleep mode of the clock-source generator power supply (the power supply in external connected PMIC or LDO).

    Best regards,