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Video pipeline in the SoC

I am working on Jacinto6 based customized board, can you please tell me what exactly mean by video pipeline in H/W.
Is it a path on the H/W for carrying video data or different.

Thank in advance.

  • Hello Kumar,

    According to descriptions in TRM, video pipeline may be considered as internal bus. It is used for transfer of video data between different IP modules in SoC. 

    #Q: Is it a path on the H/W for carrying video data 

    Yes, it may define with such description. 

    See the example:

    Display controller: Reads and displays the encoded pixel data stored in memory and writes the output of one of the overlays or one of the pipelines into the system memory. The display controller supports the following components:
    – Three video pipelines, one graphic pipeline, and one write-back pipeline.

    Three identical video pipelines are available, VID1, VID2, and VID3. Each video pipeline is connected to its video FIFO controller for the input port and to the four overlay managers, LCD1, LCD2, LCD3, and TV or WB pipeline.

    Jacinto 6 has following subsystems for video processing:

    – Video Processing subsystem (VPE)
    – Video Input Capture (VIP)

    – Two Embedded Vision Engine (EVE) subsystems

    – 3D-graphics processing unit (GPU) subsystem, including POWERVRTM SGX544 dual-core
    – 2D-graphics accelerator (BB2D) subsystem, including VivanteTM GC320 core

    – Display subsystem (DSS)

    Best regards,