Hello,
I have as design problem. I have made a design which detects a signal which compared with a reference signal which comes from an Ardino uno. The reference signal is generated by the Ardino as an block signal which is fed to a capacitor which flattens the signal to a steady voltage. By regulating the duty cycle the Ardino generates via the capacitor C5 and resistor R8 a requested voltage which is compared with the input signal (peek detector) on pin 2 of the TLLC272CDR. The design is constructed as an smith trigger and the output of the. amplifier has an positive feed back to pin 3 with resistors R9, R11 and R10.
The result of the output signal (ADC) is the blue block signal. (see attachment.) This is as expected.
The ADC signal is the input clock signal which is connected to the 74LS107AD JK-flipflop on pin 12. J and K and the inverted clear are set to high (5 Volts), so the flip-flop should toggle the output on the clock.
But.... the output signal of the flip-flop on pin 3 responds not as expected. On the negative edge of the clock signal the output should toggle. The yellow line (see attachment) shows the produced output signal of the flip-flop. Sometimes the toggle react on the negative edge of the clock as expected. Sometimes it doesn't react at all on the negative edge signal. Sometimes the toggle is been done on the positive edge of the clock, which should not be done.
It seems that the flipflop reacties random on the clock signal edges. I have already replaced the flip-flop chip as also the TLC272CDR. This did not help and it looks I have made an design error.
What did I wrong?
Regards,
Alex
