This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CD74HC4046A: Operation of CD74HC4046A phase comparator in MHz band

Part Number: CD74HC4046A
Other Parts Discussed in Thread: SN74LV4046A

Hi team

I want to use the PLL-IC at 6.78MHz.

I purchased the CD74HC4046A, which can operate at 18MHz (when Vcc = 5V ) according to the "features" on the top page of the data sheet.

So far, I have confirmed that the VCO can transmit 6.78MHz.

However, I have not yet confirmed the correct operation of the phase comparator (PC2) at 6.78MHz.

I haven't found the causes of the problem yet.

How much the frequency, which can operate correctly the PC2 without a divider?

Moreover, if PC2 could work at 6.78MHz, what is the reason of the problem?

Best Regards.

Thank you for your support!

From Yasuo.

  • Hi Yasuo,

    Can you show us a schematic of your circuit?

    What values are you using for your timing components?

    What values are you using for your loop filter?

    You said you are having issues with the circuit -- what issues are you having? Do you have a scope shot of the issue occurring?

  • Hi team.

    Thank you for your reply.

     

    Figure1 shows the schematic of my circuit.

    Figure2 shows the operation result of the circuit (SIGin: 6.78MHz).

    My problem is that I haven't confirmed the output shown in Fig. 3 from the phase comparator yet.

     

    Best Regards.

     

    From Yasuo.

  • The PC2 output is either high, low, or high-impedance. You can see a transition to high or low, but high-impedance won't typically appear as any change on the scope -- it's just allowing the voltage to 'float' where it was for a while.

    You can see that the PCout signal on your scope is driven high after a rising edge on SIGin, so the 'high' state obviously works, however, before that we have no way of knowing the state of the output (either low or high-impedance).  I would assume high-impedance since I know how the state machine works for PC2 (described in this document: https://www.ti.com/lit/scha002)

    It looks to me like the VCO frequency is about half of what the input frequency is, maybe even less. Can you get a scope shot a little more zoomed out so we can see maybe 10 or 20 cycles of the input clock? I can see that the VCOin is starting to increase here, but I can't see enough to be sure of exactly what's going on.

  • Also - I would recommend to increase your loop filter's time constant by 10x to improve stability. I would try replacing the 22pF capacitor with a 220pF capacitor (or 100pF... something in the 100's of pF), which will put your cutoff frequency at about 73 kHz and will reduce the response time -- which will also help the PLL to lock. and reduce variation.

  • Hi team.

     

    I was able to understand the high impedance state of the phase comparator.

     

    Thank you very much.

     

    Also, I have retaken the experimental data according to your indication.

     

    Experimental data are shown in Figures 1 through 4.

     

    The difference between Figures 1, 2 and Figures 3, 4 is the value of the filter capacitor.

     

    The experimental conditions are the same as the previous data.

     

    Best Regards.

     

    From Yasuo.

     

  • Hi Yasuo,

    It looks like the increased loop filter value has significantly improved the lock:

    Since PC2 is edge controlled, I marked all the rising edges of the input waveforms to the phase comparator:

    PC2 works by changing the output state between LOW - Hi-Z - HIGH, and each edge causes either an increase (-->) or a decrease (<--) in state.

    On the fourth clock pulse in the waveform, you can see that the PC2 output switches into the high state:

    Shortly after that, the output switches back into high impedance and we can see it floating downwards:

    This is the expected operation of the device -- it is trying to lock the VCO to the input frequency.

    After this, the lock starts to drift:

    The blue circled edges push PC2 back into the HIGH output state, which will repeat the process and recover the lock.

    Further increasing your loop filter capacitance will improve the performance (reducing drift).

    If the exact phase match is not a requirement, I would recommend to switch to PC1, which is much simpler and will keep the output locked to the correct frequency, although it will produce a constant phase shift between the signal and VCO output.

    Also, you could try our newer version of this device, the SN74LV4046A, which has better linearity and reduced delays