My customers request:
I have to handle two 1.8V-SPI-Interfaces (each with 4 signals: CLK,CS,MOSI,MISO) between two components, which are sometimes partially powered. During “power-save-mode”
In order to fulfill the SPI master write timings the skew between the channels is important. The SN74AUC125 is an option. The propagation specification is from 0.5 to 2.1ns. I couldn’t find anything within the datasheet. Therefore following questions:
- Is there a specification for the skew between the 4 channels of one SN74AUC125?
- Do you have a better suggestion (e.g. another buffer type) to solve the problem?
BR
Frank